ATmega329P Atmel Corporation, ATmega329P Datasheet - Page 42

• Manufacturer Part Number: ATmega329P
• Manufacturer: Atmel Corporation

Specifications of ATmega329P

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

9.11
9.11.1
9.11.2
8021G–AVR–03/11
Register Description
SMCR – Sleep Mode Control Register
MCUCR – MCU Control Register
The Sleep Mode Control Register contains control bits for power management.
• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in
Table 9-2.
Note:
• Bit 1 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see
on page
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to
zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
Bit
0x35 (0x55)
Read/Write
Initial Value
Bit
0x33 (0x53)
Read/Write
Initial Value
SM2
0
0
0
0
1
1
1
1
1. Standby mode is only recommended for use with external crystals or resonators.
37. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
JTD
R/W
Sleep Mode Select
7
0
R
7
–
0
SM1
0
0
1
1
0
0
1
1
BODS
R/W
6
0
R
6
–
0
BODSE
R/W
5
0
R
5
–
0
SM0
0
1
0
1
0
1
0
1
PUD
R/W
R
4
–
0
4
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
Reserved
Reserved
Standby
Reserved
SM2
R/W
3
0
R
3
–
0
(1)
ATmega329P/3290P
SM1
R/W
2
0
R
2
–
0
SM0
R/W
Table
IVSEL
R/W
1
0
1
0
9-2.
R/W
IVCE
SE
R/W
0
0
0
0
Table 9-1
MCUCR
SMCR
42