ATmega329PA Atmel Corporation, ATmega329PA Datasheet

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ATmega329PA

Manufacturer Part Number
ATmega329PA
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega329PA

Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Features
High Performance, Low Power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
QTouch
JTAG (IEEE std. 1149.1 compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Speed Grade:
Temperature range:
Ultra-Low Power Consumption (picoPower devices)
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at16MHz (ATmega169A/169PA/649A/649P)
– Up to 20 MIPS Throughput at 20MHz (ATmega329A/329PA/3290A/3290PA/6490A/6490P)
– On-Chip 2-cycle Multiplier
– In-System Self-programmable Flash Program Memory
– EEPROM
– Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix acquisition
– Up to 64 sense channels
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– 4 x 25 Segment LCD Driver
– 4 x 40 Segment LCD Driver (ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P)
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
– 54/69 Programmable I/O Lines
– 64/100-lead TQFP, 64-pad QFN/MLF, and 64-pad DRQFN
– ATmega169A/169PA/649A/649P:
– ATmega3290A/3290PA/6490A/6490P:
– -40°C to 85°C Industrial
– Active mode:
– Power-down Mode:
– Power-save Mode:
(ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P)
• 16Kbytes (ATmega169A/ATmega169PA)
• 32Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)
• 64Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)
• 512bytes (ATmega169A/ATmega169PA)
• 1Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)
• 2Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)
• 1Kbytes (ATmega169A/ATmega169PA)
• 2Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA)
• 4Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P)
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
• 0 - 16MHz @ 1.8 - 5.5V,
• 0 - 20MHz @ 1.8 - 5.5V,
• 1MHz, 1.8V: 215µA
• 32kHz, 1.8V: 8µA (including Oscillator)
• 32kHz, 1.8V: 25µA (including Oscillator and LCD)
• 0.1µA at 1.8V
• 0.6µA at 1.8V (Including 32kHz RTC)
• 750nA at 1.8V
®
library support
®
AVR
®
8-Bit Microcontroller
(1)
8-bit Atmel
Microcontroller
with 16/32/64K
Bytes In-System
Programmable
Flash
ATmega169A
ATmega169PA
ATmega329A
ATmega329PA
ATmega649A
ATmega649P
ATmega3290A
ATmega3290PA
ATmega6490A
ATmega6490P
8284D–AVR–6/11

Related parts for ATmega329PA

ATmega329PA Summary of contents

Page 1

... MIPS Throughput at 20MHz (ATmega329A/329PA/3290A/3290PA/6490A/6490P) – On-Chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – In-System Self-programmable Flash Program Memory • 16Kbytes (ATmega169A/ATmega169PA) • 32Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA) • 64Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P) – EEPROM • 512bytes (ATmega169A/ATmega169PA) • 1Kbytes (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA) • 2Kbytes (ATmega649A/ATmega649P/ATmega6490A/ATmega6490P) – ...

Page 2

... ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1. Pin Configurations 1.1 Pinout - 64A (TQFP) and 64M1 (QFN/MLF) Figure 1-1. Pinout ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 (SCK/PCINT9) PB1 11 (MOSI/PCINT10) PB2 12 (MISO/PCINT11) PB3 ...

Page 3

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1.2 Pinout - 100A (TQFP) Figure 1-2. Pinout ATmega3290A/ATmega3290PA/ATmega6490A/ATmega6490P 1 LCDCAP 2 (RXD/PCINT0) PE0 3 (TXD/PCINT1) PE1 4 (XCK/AIN0/PCINT2) PE2 5 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 8 (DO/PCINT6) PE6 9 (CLKO/PCINT7) PE7 10 VCC 11 GND ...

Page 4

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1.3 Pinout - 64MC (DRQFN) Figure 1-3. Table 1-1. A1 PE0 A9 B1 VLCDCAP B8 A2 PE1 A10 B2 PE2 B9 A3 PE3 A11 B3 PE4 B10 A4 PE5 A12 B4 PE6 B11 A5 PE7 A13 B5 PB0 B12 ...

Page 5

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 2. Overview The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a low-power CMOS 8-bit microcon- troller based on the Atmel AVR ® ® the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 ...

Page 6

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P provides the following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K bytes EEPROM, 1K/2K/4K byte SRAM, ...

Page 7

... ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 2.2 Comparison Between ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P Table 2-1. Differences between: ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P Device Flash ATmega169A 16Kbyte ATmega169PA 16Kbyte ATmega329A 32Kbyte ATmega329PA 32Kbyte ATmega3290A 32Kbytes ATmega3290PA 32Kbyte ATmega649A 64Kbyte ATmega649P 64Kbyte ATmega6490A 64Kbyte ATmega6490P 64Kbyte 8284D–AVR–6/11 EEPROM RAM 512Bytes 1Kbyte ...

Page 8

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 2.3 Pin Descriptions The following section describes the I/O-pin special functions. 2.3 Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7...PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each ...

Page 9

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Port D also serves the functions of various special features of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on 79. 2.3.7 Port E (PE7...PE0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port ...

Page 10

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. ...

Page 11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM ...

Page 12

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, ...

Page 13

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as ...

Page 14

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more ...

Page 15

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7.5 General Purpose Register File The Register File is optimized for ...

Page 16

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 7.5.1 The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, ...

Page 17

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 7.6.1 SPH and SPL – Stack pointer High and Stack Pointer Low Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value Note: 7.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU ...

Page 18

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 7.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must ...

Page 19

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 C Code Example ...

Page 20

... On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are bits wide, the Flash is organized (ATmega169A/169PA) and 16/32K x 16 (ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA/ATmega649A/ATmega649P/A Tmega6490A/ATmega6490P). For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. ...

Page 21

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8.2 SRAM Data Memory Figure 8-2 The ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space ...

Page 22

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 8-3. 8.3 EEPROM Data Memory The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P contains 512/1K/2K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at ...

Page 23

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit ...

Page 24

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that ...

Page 25

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Assembly Code Example EEPROM_read: C Code Example unsigned char EEPROM_read(unsigned int uiAddress 8.3.2 EEPROM Write During Power-down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, ...

Page 26

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, ...

Page 27

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8.6 Register Description 8.6.1 EEARH and EEARL – EEPROM Address Register ATmega169A/169PA Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:9 – Reserved These bits are reserved and will always be read as zero. • Bits 8:0 ...

Page 28

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8.6.3 EEDR – EEPROM Data Register Bit 0x20 (0x40) Read/Write Initial Value • Bits 7:0 – EEDR7:0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address ...

Page 29

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8.6.6 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 8.6.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write Initial Value 8284D–AVR–6/ MSB R/W R/W R/W R/W 0 ...

Page 30

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by ...

Page 31

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this ...

Page 32

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.4 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. The device is shipped with the CKDIV8 Fuse ...

Page 33

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in the manufacturer should be used. Figure 9-2. The Oscillator can operate in three different modes, each optimized for a specific frequency ...

Page 34

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 9-6. CKSEL0 Notes: 9.6 Low-frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal. When selecting crystals, load capacitance and crystal’s Equivalent Series Resistance, ESR must be taken into ...

Page 35

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The Low-frequency Crystal Oscillator provides an internal load capacitance, each TOSC pin. Table 9-9. ATmega169A/169PA/329A/329PA/3290A /3290PA/649A/649P/6490A/6490P The capacitance (Ce + Ci) needed at each TOSC pin can be calculated by using: where optional external capacitors as ...

Page 36

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 9-3. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-13. Table 9-12. ATmega169A/169PA/649A/649P ATmega329A/329PA/3290A/3290PA/6490A/6490P Table 9-13. SUT1.. When applying an external clock ...

Page 37

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.9 Timer/Counter Oscillator ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See Crystal Oscillator” on page 34 ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, ...

Page 38

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.11 Register Description 9.11.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations ...

Page 39

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled ...

Page 40

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 10. Power Management and Sleep Modes 10.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving- power. The AVR provides various sleep modes allowing the user to tailor the power consumption to ...

Page 41

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures ...

Page 42

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P interrupt on INT0 pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from ...

Page 43

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 10.10 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be ...

Page 44

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 10.10.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock ...

Page 45

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 10.11 Register Description 10.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, ...

Page 46

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically ...

Page 47

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a ...

Page 48

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 11-1. Reset Logic BODLEVEL [2..0] 11.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used ...

Page 49

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 11-2. MCU Start-up, RESET Tied to V TIME-OUT INTERNAL Figure 11-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than ...

Page 50

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 11.2.3 Brown-out Detection ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P has an On-chip Brown-out Detection (BOD) circuit for monitoring the fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis ...

Page 51

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 11.3 Internal Voltage Reference ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P features an inter- nal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.3.1 Voltage Reference Enable Signals and ...

Page 52

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 11-7. Watchdog Timer 11.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 11.4.2 Safety Level 1 In ...

Page 53

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 11.5 Register Description 11.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit ...

Page 54

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be ...

Page 55

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. ...

Page 56

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 12. Interrupts 12.1 Overview ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 12-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 0x0036 0x0037 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 0x382C/0x782C ; 0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start 0x382F/0x782F 0x3830/0x7830 0x3831/0x7831 0x3832/0x7832 0x3833/0x7833 12.2.1 Moving Interrupts Between Application and Boot Space he General Interrupt Control Register controls the placement of the Interrupt Vector table, see ”MCUCR – MCU Control Register” on ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 12.3 Register Description 12.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value Note: • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 13. External Interrupts 13.1 Overview The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins that, if enabled, the interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as outputs. This ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 13.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 13-1. Pin Change Interrupt 13.3 Register Description 13.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 13-1. ISC01 13.3.2 EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • Bit 7 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. 13.3.3 EIFR – External Interrupt Flag Register Bit 0x1C (0x3C) Read/Write Initial Value • ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 13.3.4 PCMSK3 – Pin Change Mask Register 3 Bit (0x73) Read/Write Initial Value • Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30...24 Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT30:24 ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 14.2 Ports as General Digital I/O ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 14-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Assembly Code Example C Code Example unsigned char i; Note: 14.2.5 Digital Input Enable and Sleep Modes As shown in input of the Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.2.6 Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be present in ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3.1 Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller. Table 14-3. Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Table 14-4 shown in Table 14-4. ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 14.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-6. Port Pin PB7 PB6 PB5 PB4 ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 bit PCINT8, ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3.3 Alternate Functions of Port C The Port C has an alternate function as SEG for the LCD Controller. Table 14-9. Port Pin PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The alternate pin configuration is as follows: • ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 14.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-13 shown in Table 14-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI (1) AIO (2) AIO 1. 2. Table 14-14. Overriding Signals for Alternate Functions in PD3:PD0 ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 14-15. Port E Pins Alternate Functions Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 • PCINT7 – Port E, Bit ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 oper- ates ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-17. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 14.3.6 Alternate Functions of Port F The Port F has an alternate function as analog input ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-20. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 14.3.7 Alternate Functions of Port G The alternate pin configuration is as follows: Table 14-21. Port G ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • SEG – Port G, Bit 2 SEG, LCD front plane 4/4. • SEG – Port G, Bit 1 SEG, Segment driver 17/13. • SEG – Port G, Bit 0 SEG, LCD front plane 18/14. Table 14-21 shown in ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-23. Overriding Signals for Alternate Functions in PG3:0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI (1) AIO (2) AIO 1. 2. 14.3.8 Alternate Functions of Port H Port H is only present in ...

Page 88

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • PCINT22/SEG – Port H, Bit 6 PCINT22, Pin Change Interrupt Source 22: The PH6 pin can serve as an external interrupt source. SEG, LCD front plane 37. • PCINT21/SEG – Port H, Bit 5 PCINT21, Pin Change Interrupt ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-25 shown in Table 14-25. Overriding Signals for Alternate Functions in PH7:4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI (1) AIO (2) AIO 1. 2. Table 14-26. Overriding Signals for Alternate Functions in ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3.9 Alternate Functions of Port J Port J is only present in ATmega3290A/3290PA/6490A/6490P. The alternate pin configuration is as follows: Table 14-27. Port J Pins Alternate Functions Port Pin PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 The alternate pin ...

Page 91

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • PCINT28/SEG – Port J, Bit 4 PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external interrupt source. SEG, LCD front plane 29. • PCINT27/SEG – Port J, Bit 3 PCINT27, Pin Change Interrupt ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-28 on page 92 the overriding signals shown in Table 14-28. Overriding Signals for Alternate Functions in PJ7:4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 14-29. Overriding Signals for Alternate Functions ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.4 Register Description 14.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if ...

Page 94

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.4.8 PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 14.4.9 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 14.4.10 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.4.16 PINE – Port E Input Pins Address Bit 0x0C (0x2C) Read/Write Initial Value 14.4.17 PORTF – Port F Data Register Bit 0x11 (0x31) Read/Write Initial Value 14.4.18 DDRF – Port F Data Direction Register Bit 0x10 (0x30) Read/Write ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.4.24 DDRH – Port H Data Direction Register Bit (0xD9) Read/Write Initial Value 14.4.25 PINH – Port H Input Pins Address Bit (0xD8) Read/Write Initial Value 14.4.26 PORTJ – Port J Data Register Bit (0xDD) Read/Write Initial Value 14.4.27 ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15. 8-bit Timer/Counter0 with PWM 15.1 Features • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler ...

Page 98

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A Flag or ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 15-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out- ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P the pin is set to output. The waveform generated will have a maximum frequency when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 15-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up- counting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 15-11 Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx ...

Page 109

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Note: Table 15-5 rect PWM mode. Table 15-5. COM0A1 Note: • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 15-6. CS02 ...

Page 111

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15.9.3 OCR0A – Output Compare Register A Bit 0x27 (0x47) Read/Write Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an ...

Page 112

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16. 16-bit Timer/Counter1 16.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 16-1. 16-bit Timer/Counter Block Diagram Note: 16.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P tion “16.7” on page 121. Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the ...

Page 115

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each ...

Page 116

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how atomic read of the TCNT1 Register contents. Reading ...

Page 117

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example ...

Page 118

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is ...

Page 119

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that ...

Page 120

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is ...

Page 121

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 16.7 Output Compare Units The 16-bit comparator continuously ...

Page 122

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x ...

Page 123

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the ...

Page 124

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P OC1x Register performed on the next compare match. For compare output actions in the non-PWM modes refer to page 134, and for phase correct and phase and frequency correct PWM refer to page 134. A change ...

Page 125

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 16-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to ...

Page 126

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is ...

Page 127

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the ...

Page 128

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter ...

Page 129

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope ...

Page 130

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP ...

Page 131

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units ...

Page 132

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 16-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 ...

Page 133

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit ...

Page 134

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 16-3 PWM mode. Table 16-3. COM1A1/COM1B1 Note: Table 16-4 correct or the phase and frequency correct, PWM mode. Table 16-4. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the ...

Page 135

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 16-5. Waveform Generation Mode Bit Description WGM12 Mode WGM13 (CTC1) (PWM11 ...

Page 136

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – ...

Page 137

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 16.11.4 TCNT1H and TCNT1L – ...

Page 138

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog ...

Page 139

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 17. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source The Timer/Counter can be clocked ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 17.4 Register Description 17.4.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 17-2. COM0A1 Table 17-3 mode. Table 17-3. COM0A1 Note: Table 17-4 rect PWM mode. Table 17-4. COM0A1 Note: 8284D–AVR–6/11 Compare Output Mode, non-PWM Mode COM0A0 Description ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 17-5. CS02 external pin modes are used ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 17.4.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 17.4.6 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 18-2 shows a block diagram of the counter and its surrounding environment. Figure 18-2. Counter Unit Block Diagram Signal description (internal signals): count ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page Figure 18-3 Figure 18-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare unit, independently of ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P tion Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 18-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2A to toggle its logical level on each compare match (COM2A[1:0] = 1). The waveform generated will have a maximum frequency ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2A[1:0] ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 18-9 Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (f Figure 18-10 Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f Figure 18-11 on page 158 8284D–AVR–6/11 shows the same timing data, but with the prescaler enabled. ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- 18.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2A, TCNT2, or ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.9.1 Timer/Counter Prescaler Figure 18-12. Prescaler for Timer/Counter2 TOSC1 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.10 Register Description 18.10.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P When OC2A is connected to the pin, the function of the COM2A[1:0] bits depends on the WGM2[1:0] bit setting. bits are set to a normal or CTC mode (non-PWM). Table 18-3. COM2A1 Table 18-4 PWM mode. Table 18-4. COM2A1 ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 18-6. CS22 18.10.2 TCNT2 – Timer/Counter Register Bit (0xB2) Read/Write Initial Value The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil- lator 1 (TOSC1) ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.10.6 TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 0x17 (0x37) Read/Write Initial Value • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 19. SPI – Serial Peripheral Interface 19.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 19-1. SPI Block Diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in 168. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when ...

Page 168

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8284D–AVR–6/11 (1) ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 19.3 SS Pin Functionality 19.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 19-3. SPI Transfer Format with CPHA = 0 Figure 19-4. SPI Transfer Format with CPHA = 1 8284D–AVR–6/11 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 19.5 Register Description 19.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P program memory and EEPROM downloading or uploading. See serial programming and verification. 19.5.3 SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20. USART0 20.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 20-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.2.1 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 20-2. .Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc 20.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f OSC UBRRn Some examples of UBRRn values for some system clock frequencies are found in page ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.3.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change ...

Page 182

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A IDLE The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example USART_Init: C Code Example #define FOSC 1843200 // Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P contains data to be transmitted that has not yet been moved into the Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable ...

Page 187

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code example shows a simple USART receive function that handles both nine bit characters and the status bits. Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communi- cation activity). Figure 20-5. Start Bit Sampling When the clock recovery logic detects a high (idle) to low (start) transition on the RxD ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-2. # (Data+Parity Bit) Table 20-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.10 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRRn settings in UBRRn values which yield an actual baud rate ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-7. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.11 Register Description 20.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or ...

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ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The ...

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