ATmega48 Atmel Corporation, ATmega48 Datasheet
ATmega48
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Page 1
... Temperature range: ° ° – - • Speed grade: – ATmega48V/88V/168V 4MHz @ 1.8V - 5.5V 10MHz @ 2.7V - 5.5V – ATmega48/88/168 10MHz @ 2.7V - 5.5V 20MHz @ 4.5V - 5.5V • Low power consumption – Active mode: 250µA at 1MHz, 1.8V 15µA at 32kHz, 1.8V (including oscillator) – Power-down mode: 0.1µA at 1.8V Note: 1. See “Data retention” on page 8 ® ...
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... Pin configurations Figure 1-1. Pinout Atmel ATmega48/88/168. TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 28 MLF Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 VCC 3 GND 4 (PCINT6/XTAL1/TOSC1) PB6 5 (PCINT7/XTAL2/TOSC2) PB7 6 (PCINT21/OC0B/T1) PD5 7 NOTE: Bottom pad should be soldered to ground. ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up 2545T–AVR–05/11 “System clock and clock options” on page Table 29-3 on page ATmega48/88/168 “Alternate functions of port B” on page 27. 307. Shorter pulses are not guaran- “Alternate functions of port C” on page ...
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... In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 2545T–AVR–05/11 , even if the ADC is not used. If the ADC is used, it should be connected ATmega48/88/168 “Alternate functions of port D” on page . CC CC ...
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... Overview The Atmel ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
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... Atmel ATmega48/88/168 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega48/88/168 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu- lators, and Evaluation kits ...
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... ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...
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... The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide 2545T–AVR–05/11 ATmega48/88/168 - also available for download from the Atmel website. 8 ...
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... The program memory is In-System Reprogrammable Flash memory. 2545T–AVR–05/11 Block diagram of the AVR architecture. Program Flash counter program memory Instruction register Instruction decoder Control lines ATmega48/88/168 Data bus 8-bit Status and control Interrupt unit general purpose SPI registrers unit Watchdog ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega48/88/168 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... R/W R/W R/W R “Instruction Set Description” for detailed information. ⊕ V “Instruction Set Description” for detailed information. Description” for detailed information. Description” for detailed information. ATmega48/88/168 R/W R/W R/W R instruction set reference. “Instruction ...
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... R15 working R16 registers R17 … R26 R27 R28 R29 R30 R31 Figure 7-2, each register is also assigned a data memory address, mapping them ATmega48/88/168 “Instruction Set 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register low byte 0x1B ...
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... AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 2545T–AVR–05/11 The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D R31 (0x1F) ATmega48/88/168 Figure 7- R26 (0x1A R28 (0x1C R30 (0x1E) instruction set reference for details). ...
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... Register File single clock cycle an ALU Single cycle ALU operation. T1 clk CPU Total execution time Result write back ATmega48/88/168 SP12 SP11 SP10 SP9 SP4 ...
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... CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. 2545T–AVR–05/11 for details. “Interrupts” on page 56 “Boot loader support – Read-while-write self-programming, Atmel 269. ATmega48/88/168 “Memory program- “Interrupts” on page 56. The list also for more information. 15 ...
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... Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2545T–AVR–05/11 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ; set Global Interrupt Enable ATmega48/88/168 16 ...
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... Overview This section describes the different memories in the Atmel ATmega48/88/168. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega48/88/168 features an EEPROM Memory for data storage. All three mem- ory spaces are linear and regular ...
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... Figure 8-1. Figure 8-2. 2545T–AVR–05/11 Program memory map, Atmel ATmega48. Program memory Application flash section Program memory map, Atmel ATmega88 and Atmel ATmega168. Program memory Application flash section Boot flash section ATmega48/88/168 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF 18 ...
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... SRAM data memory Figure 8-3 The ATmega48/88/168 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc- tions can be used ...
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... EEPROM data memory The Atmel ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory orga- nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... The I/O space definition of the Atmel ATmega48/88/168 is shown in page 343. All ATmega48/88/168 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Initial value • Bits 15..9 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 256/512/512 bytes EEPROM space ...
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... EEPROM mode bits. Programming EEPM0 time Operation 0 3.4ms Erase and write in one operation (atomic operation) 1 1.8ms Erase only 0 1.8ms Write only 1 – Reserved for future use for details about Boot programming. ATmega48/88/168 “Boot 23 ...
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... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 2545T–AVR–05/11 EEPROM programming time. Number of calibrated RC oscillator cycles 26,368 ATmega48/88/168 Table 8-2 lists the typical pro- Typical programming time 3.3ms 24 ...
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... EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret /* Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); ATmega48/88/168 25 ...
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... Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR MSB R/W R/W R MSB R/W R/W R MSB R/W R/W R ATmega48/88/168 R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R ...
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... AVR clock I/O control unit clk ASY System clock prescaler Clock multiplexer Timer/counter External clock oscillator is halted, TWI address recognition in all sleep modes. I/O ATmega48/88/168 CPU core RAM clk ADC clk CPU clk FLASH Reset logic Watchdog timer Source clock Watchdog clock Watchdog ...
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... ASY Device clocking options select 1. For all fuses “1” means unprogrammed while “0” means programmed. to start oscillating and a minimum number of oscillating CC , the device issues an internal reset with a time-out delay (t CC ATmega48/88/168 (1) . CKSEL3..0 1111 - 1000 0111 - 0110 0101 - 0100 ...
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... Number of watchdog oscillator cycles. = 5.0V) Typical time-out (V CC 0ms 0ms 4.1ms 4.3ms 65ms 69ms before it releases the reset, and the time-out delay CC 31. Table 9-3 on page ATmega48/88/168 315. = 3.0V) Number of cycles (4,096) 8K (8,192) Figure 9-2 on page 30. Either a quartz 30. For ceramic resonators, the capacitor val- . The “ ...
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... Start-up times for the low power crystal oscillator clock selection. Start-up time from power-down and power-save 258CK 258CK 1KCK 1KCK 1KCK ATmega48/88/168 XTAL2 XTAL1 GND (3) . CKSEL3..1 – ...
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... C1 and C2 (pF) 0 8MHz frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency by eight. It must be ensured that the resulting divided clock meets the frequency specification of the device. ATmega48/88/168 Additional delay from reset (V = 5.0V) ...
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... These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. ATmega48/88/168 XTAL2 XTAL1 ...
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... Reserved 1. These options should only be used if frequency stability at start-up is not important for the application. 34. If selected, it will operate with no external components. During reset, Table 29-1 on page 306. “Calibration byte” on page ATmega48/88/168 Figure 9-2 on page 30. When this Additional delay from reset (V = 5.0V) ...
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... Start-up times for the 128kHz internal oscillator. Start-up time from power-down and power-save 6CK 6CK 6CK Reserved 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4.1ms to ensure programming mode can be entered. ATmega48/88/168 (1)(2) . CKSEL3..0 0010 ), the CKDIV8 CC Additional delay from reset ( ...
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... External clock drive configuration PB7 EXTERNAL CLOCK SIGNAL Start-up times for the external clock selection. Start-up time from power-down and power-save 6CK 6CK 6CK Reserved ATmega48/88/168 CKSEL3..0 0000 XTAL2 XTAL1 GND Additional delay from reset (V = 5.0V) SUT1..0 CC 14CK 14CK + 4.1ms 14CK + 65ms “ ...
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... System clock prescaler The Atmel ATmega48/88/168 has a system clock prescaler, and the system clock can be divided by setting the to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... R/W R/W Device specific calibration value 306. The application software can write this register to change the oscilla CLKPCE – – – R 38. ATmega48/88/168 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W Table 29-1 on page CLKPS3 CLKPS2 CLKPS1 CLKPS0 ...
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... ATmega48/88/168 CLKPS0 Clock division factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 38 ...
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... This sleep mode basically halts clk 2545T–AVR–05/11 presents the different clock systems in the Atmel ATmega48/88/168, and Active clock domains and wake-up sources in the different sleep modes. Active clock domains ...
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... Timer/Counter2 interrupt enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set. 2545T–AVR–05/11 1. Timer/Counter2 will only keep running in asynchronous mode, see PWM and asynchronous operation” on page 140 “Clock sources” on page ATmega48/88/168 (1) , and the Watchdog to continue operating , clk , and clk , while allowing the other ...
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... Power reduction register” on page “Power-down supply current” on page 323 “Analog comparator” on page 241 ATmega48/88/168 44, provides for examples. In all other “Analog-to-digital converter” on page 244 for details on how to configure the analog ...
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... Digital CC “DIDR1 – Digital input disable register 1” on page 243 for details. ATmega48/88/168 for details on how to for details on how to configure the watchdog timer. ) are stopped, the input buffers of the device will ...
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... Initial value • Bits 7..4 Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bits 3..1 – SM2..0: Sleep mode select bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 10-2 ...
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... Bit 4 - Res: Reserved bit This bit is reserved in Atmel ATmega48/88/168 and will always read as zero. • Bit 3 - PRTIM1: Power reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • ...
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... For the Atmel ATmega168, the instruction placed at the reset vector must be a JMP – absolute jump – instruction to the reset handling routine. For the Atmel ATmega48 and Atmel ATmega88, the instruction placed at the reset vector must be an RJMP – relative jump – ...
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... The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT RESET ATmega48/88/168 DATA BUS MCU status register (MCUSR) Delay counters CK TIMEOUT 307. The POR is activated whenever CC. 46 ...
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... RSTDISBL fuse, see Figure 11-4. External reset during operation. 11.5 Brown-out detection The Atmel ATmega48/88/168 has an on-chip brown-out detection (BOD) circuit for monitoring the V CC BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free brown-out detection. The hysteresis on the detection level should be interpreted as ...
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... Figure 11-6. Watchdog system reset during operation. 11.7 Internal voltage reference The Atmel ATmega48/88/168 features an internal bandgap reference. This reference is used for brown-out detection, and it can be used as an input to the analog comparator or the ADC. 11.7.1 Voltage reference enable signals and start-up time The voltage reference has a start-up time that may influence the way it should be used ...
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... Possible hardware fuse watchdog always on (WDTON) for fail-safe mode Figure 11-7. Watchdog timer. The Atmel ATmega48/88/168 has an enhanced watchdog timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - watchdog timer reset - instruction to restart the counter before the time-out value is reached ...
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... The following code example shows one assembly and one C function for turning off the watch- dog timer. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 2545T–AVR–05/11 ATmega48/88/168 50 ...
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... Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. See ”About code examples” on page 8. ATmega48/88/168 51 ...
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... WDTCSR, r16 ; -- Finished setting new values, used 2 cycles - ; Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. See ”About code examples” on page 8. ATmega48/88/168 52 ...
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... Initial value • Bit 7..4: Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 3 – WDRF: Watchdog system reset flag This bit is set if a watchdog system reset occurs. The bit is reset by a power-on reset writ- ing a logic zero to the flag. • ...
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... Interrupt mode 1 0 System reset mode Interrupt and system reset 1 1 mode x x System reset mode 1. WDTON fuse set to “0“ means programmed and “1“ means unprogrammed. ATmega48/88/168 Action on time-out None Interrupt Reset Interrupt, then go to system reset mode Reset 54 ...
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... ATmega48/88/168 Number of Typical time-out (2048) cycles 4K (4096) cycles 8K (8192) cycles Reserved Table 11- = 5.0V 16ms 32ms 64ms 0.125s 0.25s 0.5s 1.0s 2.0s 4.0s 8.0s 55 ...
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... Each interrupt vector occupies two instruction words in ATmega168, and one instruction word in ATmega48 and ATmega88 • ATmega48 does not have a separate boot loader section. In ATmega88 and ATmega168, the reset vector is affected by the BOOTRST fuse, and the interrupt vector start address is affected by the IVSEL bit in MCUCR 12 ...
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... Table 12-1. Reset and interrupt vectors in ATmega48. (Continued) Vector no. Program address 22 0x015 23 0x016 24 0x017 25 0x018 26 0x019 The most typical and general program setup for the reset and interrupt vector addresses in the Atmel ATmega48 is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 ...
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... When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot flash section. The address of each Interrupt Vector will then be the address in this table added to the start address of the boot flash section. shows reset and interrupt vectors placement for the various combina- ATmega48/88/168 58 ...
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... Main program start out SPH,r16 ldi r16, low(RAMEND) out SPL,r16 sei <instr> xxx ATmega48/88/168 (1) . Interrupt vectors start address 0x001 Boot reset address + 0x001 0x001 Boot reset address + 0x001 Table 27-6 on page 281. For the BOOTRST Fuse “1” Comments ...
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... EXT_INT0 rjmp EXT_INT1 ... ... rjmp SPM_RDY RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ATmega48/88/168 Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ...
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... Atmel ATmega168” on page 269. 2. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot flash section. The address of each Interrupt Vector will then be the address in this table added to the start address of the boot flash section. ATmega48/88/168 ; Enable interrupts 61 ...
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... ADC jmp EE_RDY jmp ANA_COMP jmp TWI jmp SPM_RDY ldi r16, high(RAMEND); Main program start ATmega48/88/168 (1) . Interrupt vectors start address 0x001 Boot reset address + 0x0002 0x001 Boot reset address + 0x0002 Table 27-6 on page 281. For the BOOTRST fuse “1” Comments ...
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... Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx ATmega48/88/168 ; Set Stack Pointer to top of RAM ; Enable interrupts Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ; IRQ0 Handler ...
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... IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the status register is unaffected by the automatic disabling. Note: This bit is not available in Atmel ATmega48. 2545T–AVR–05/11 jmp RESET ...
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... IVSEL description above. See code example below. Assembly code example Move_interrupts: C code example void Move_interrupts(void) { uchar temp; } This bit is not available in Atmel ATmega48. 2545T–AVR–05/11 ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ...
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... Figure 13-1. Timing of pin change interrupts. 2545T–AVR–05/11 27. Low level interrupt on INT0 and INT1 is detected asynchro- 27. pin_lat pcint_in_(0) PCINT( pin_sync LE clk PCINT(0) in PCMSK(x) clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF ATmega48/88/168 “Clock systems Figure 13-1. 0 pcint_syn pcint_setflag PCIF x clk 66 ...
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... Initial value • Bit 7..4 – Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 3, 2 – ISC11, ISC10: Interrupt sense control 1 bit 1 and bit 0 The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre- sponding interrupt mask are set ...
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... Initial value • Bit 7..2 – Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 1 – INT1: External interrupt request 1 enable When the INT1 bit is set (one) and the I-bit in the status register (SREG) is set (one), the exter- nal pin interrupt is enabled ...
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... Initial value • Bit 7..3 - Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 2 - PCIE2: Pin change interrupt enable 2 When the PCIE2 bit is set (one) and the I-bit in the status register (SREG) is set (one), pin change interrupt 2 is enabled ...
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... Initial value • Bit 7 – Res: Reserved bit This bit is an unused bit in the Atmel ATmega48/88/168, and will always read as zero. • Bit 6..0 – PCINT14..8: Pin change enable mask 14..8 Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register description” on page 76. Refer to the individual module sections for a full description of the alternate ATmega48/88/168 Figure 14-1. Refer to “Electrical char Logic See figure "General Digital I/O" for details 87 ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 87, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega48/88/168 Figure 14-2 shows a func- PUD Q ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 14-2 on page shows a timing diagram of the synchronization when reading an externally applied pin ATmega48/88/168 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low No Tri-state (Hi-Z) No Output low (sink) No Output high (source) 72, the PINxn Register bit and the preced- ...
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... SYNC LATCH PINxn r17 Figure 14-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega48/88/168 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx ...
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... Figure 14-2 on page 72, the digital input signal can be clamped to ground at the “Alternate port functions” on page ATmega48/88/168 /2. CC 76. 75 ...
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... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega48/88/168 Figure 14-2 on page 72 PUD ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- input/output directionally. ATmega48/88/168 Fig- 77 ...
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... SS (SPI bus master slave select) OC1B (Timer/Counter1 output compare match B output) PCINT2 (pin change interrupt 2) OC1A (Timer/Counter1 output compare match A output) PCINT1 (pin change interrupt 1) ICP1 (Timer/Counter1 input capture input) CLKO (divided system clock output) PCINT0 (pin change interrupt 0) ATmega48/88/168 Table 14-3. 78 ...
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... Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source. 2545T–AVR–05/11 ATmega48/88/168 79 ...
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... AS2 + PCINT7 • PCINT6 • PCIE0 PCIE0 (INTRC + EXTCK) • INTRC • AS2 AS2 PCINT7 INPUT PCINT6 INPUT Oscillator/Clock Oscillator Output Input ATmega48/88/168 PB5/SCK/ PB4/MISO/ (1) PCINT5 PCINT4 SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • ...
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... PC3 PCINT11 (Pin Change Interrupt 11) ADC2 (ADC input channel 2) PC2 PCINT10 (pin change interrupt 10) ADC1 (ADC input channel 1) PC1 PCINT9 (pin change interrupt 9) ADC0 (ADC input channel 0) PC0 PCINT8 (pin change interrupt 8) ATmega48/88/168 PB1/OC1A/ PB0/ICP1/ PCINT1 PCINT0 ...
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... PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog power. PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt source. • ADC1/PCINT9 – Port C, bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. 2545T–AVR–05/11 ATmega48/88/168 82 ...
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... PCINT11 • PCIE1 + PCINT10 • PCIE1 + ADC3D ADC2D PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT11 INPUT PCINT10 INPUT ADC3 INPUT ADC2 INPUT ATmega48/88/168 (1) . PC4/SDA/ADC4/PCINT12 TWEN PORTC4 • PUD TWEN SDA_OUT TWEN 0 PCINT12 • PCIE1 + ADC4D PCINT12 • PCIE1 PCINT12 INPUT ...
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... PD3 OC2B (Timer/Counter2 output compare match B output) PCINT19 (pin change interrupt 19) INT0 (external interrupt 0 input) PD2 PCINT18 (pin change interrupt 18) TXD (USART output pin) PD1 PCINT17 (pin change interrupt 17) RXD (USART input pin) PD0 PCINT16 (pin change interrupt 16) ATmega48/88/168 Table 14-9. 84 ...
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... PORTD0 bit. PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source. Table 14-10 on page 86 the overriding signals shown in 2545T–AVR–05/11 and Table 14-11 on page 86 relate the alternate functions of Port D to Figure 14-5 on page 76. ATmega48/88/168 85 ...
Page 86
... OC2B ENABLE 0 OC2B 0 INT1 ENABLE + INT0 ENABLE + PCINT19 • PCIE2 PCINT18 • PCIE1 1 1 PCINT19 INPUT PCINT18 INPUT INT1 INPUT INT0 INPUT – – ATmega48/88/168 PD5/T1/OC0B/ PD4/XCK/ PCINT21 T0/PCINT20 OC0B ENABLE UMSEL OC0B XCK OUTPUT PCINT21 • ...
Page 87
... R/W R – DDC6 DDC5 DDC4 R R/W R/W R – PINC6 PINC5 PINC4 N/A N/A N/A ATmega48/88/168 – – IVSEL IVCE R R R/W R PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 ...
Page 88
... R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega48/88/168 PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 R/W R/W R/W R PIND3 PIND2 PIND1 ...
Page 89
... I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM0 bit in Timer/Counter0 module. 2545T–AVR–05/11 “Pinout Atmel ATmega48/88/168.” on page “Register description” on page “Minimizing power consumption” on page 41 ATmega48/88/168 Figure 15-1 on page 90 ...
Page 90
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. ATmega48/88/168 TOVn (Int.req.) Clock select ...
Page 91
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 ATmega48/88/168 for details. The compare match event 137. TOVn (Int.req.) Clock select Edge ...
Page 92
... PWM pulses, thereby making the output glitch-free. 2545T–AVR–05/11 94. (“Modes of operation” on page shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit comparator) top Waveform generator bottom FOCn WGMn1:0 ATmega48/88/168 94). TCNTn OCFnx (Int.req.) OCnx COMnx1:0 “Modes of 92 ...
Page 93
... PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin system reset occur, the OC0x Register is reset to “0”. 2545T–AVR–05/11 ATmega48/88/168 Figure 15-4 on page 94 shows a 93 ...
Page 94
... For detailed timing information refer to 2545T–AVR–05/11 COMnx1 Waveform COMnx0 generator FOCn clk I/O See “Register description” on page 101. Table 15-2 on page “Timer/counter timing diagrams” on page ATmega48/88/168 OCnx PORT D Q DDR 101. For fast PWM mode, refer to Table 15-4 on page 102 ...
Page 95
... Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for 2545T–AVR–05/11 OCn 1 2 ATmega48/88/168 Figure 15-5. The counter value (TCNT0) OCnx interrupt flag set (COMnx1 ...
Page 96
... OCnx ⋅ ⋅ Figure 15-6. The TCNT0 value is in the timing diagram shown as a his ATmega48/88/168 ) OCRnx OCRnx interrupt flag set OCRnx update and TOVn interrupt flag set (COMnx1 (COMnx1 OC0 96 ...
Page 97
... OCR0x and TCNT0. 2545T–AVR–05/11 Table 15-6 on page 102). The actual OC0x value will only be visible on f clk_I ----------------- - OCnxPWM ⋅ N 256 = f OC0 clk_I/O 98. The TCNT0 value is in the timing diagram shown as a histogram for ATmega48/88/168 /2 when OCR0A is set to zero. This 97 ...
Page 98
... Compare Match. The point of this transition is to guarantee symmetry around BOT- TOM. There are two cases that give a transition without Compare Match. • OCRnx changes its value from MAX, like in OCn pin value is the same as the result of a down-counting Compare Match. To ensure 2545T–AVR–05/11 ATmega48/88/168 Table 15-7 on page 103) ...
Page 99
... Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes ATmega48/88/168 ) is therefore shown MAX BOTTOM /8). clk_I/O MAX BOTTOM BOTTOM + 1 BOTTOM + 1 99 ...
Page 100
... TCNTn (CTC) OCRnx OCFnx 2545T–AVR–05/11 I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8). clk_I/O I/O Tn /8) I/O TOP - 1 ATmega48/88/168 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP /8). clk_I/O OCRnx + 2 BOTTOM + 1 100 ...
Page 101
... Set OC0A on compare match, clear OC0A at BOTTOM, 1 (inverting mode special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 96 for more details. ATmega48/88/168 COM0B0 – ...
Page 102
... Compare output mode, fast PWM mode COM0B0 Description 0 Normal port operation, OC0B disconnected 1 Reserved Clear OC0B on compare match, set OC0B at BOTTOM, 0 (non-inverting mode) Set OC0B on compare match, clear OC0B at BOTTOM, 1 (inverting mode) ATmega48/88/168 (1) . “Phase correct PWM mode” on (1) . 102 ...
Page 103
... Note: • Bits 3, 2 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform generation mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 104
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bit 3 – WGM02: Waveform generation mode See the description in the • Bits 2:0 – CS02:0: Clock select The three Clock Select bits select the clock source to be used by the Timer/Counter. 2545T– ...
Page 105
... External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R ATmega48/88/168 TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R OCR0B[7:0] R/W R/W R/W 0 ...
Page 106
... Initial value • Bits 7..3 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bit 2 – OCIE0B: Timer/counter output compare match B interrupt enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 107
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to generation mode bit description.” on page 2545T–AVR–05/11 ATmega48/88/168 Table 103. 15-8, “Waveform ...
Page 108
... I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. 2545T–AVR–05/11 “Pinout Atmel ATmega48/88/168.” on page “Register description” on page “PRR – Power reduction register” on page 44 ATmega48/88/168 Figure 16-1 on page 109 ...
Page 109
... Count Clear Control logic Direction Timer/counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Table 14-3 on page 78 1. Refer to Figure 1-1 on page 2, Timer/Counter1 pin placement and description. ATmega48/88/168 (1) . TOVn (Int.req.) Clock select clk Tn Edge detector TOP BOTTOM (From prescaler OCnA (Int.req.) Waveform ...
Page 110
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 register. The assignment is dependent of the mode of operation. ATmega48/88/168 (See 110 ...
Page 111
... For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega48/88/168 111 ...
Page 112
... For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega48/88/168 112 ...
Page 113
... For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. “Timer/Counter0 and Timer/Counter1 prescalers” on page ATmega48/88/168 137. 113 ...
Page 114
... The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of operation” on page ATmega48/88/168 TOVn (Int.req.) Clock select Edge detector clk Tn Control logic (From prescaler) TOP BOTTOM 119 ...
Page 115
... DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit register) WRITE ACO* ACIC* Analog comparator ICPn 110. ATmega48/88/168 Figure 16-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit counter) ICNC ICES Noise Edge ICFn (Int.req.) canceler detector “ ...
Page 116
... The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com- 2545T–AVR–05/11 ATmega48/88/168 (Figure 17-1 on page 137). The edge detector is also 116 ...
Page 117
... DATA BUS TEMP (8-bit) OCRnxH buffer (8-bit) OCRnxL buffer (8-bit) OCRnx buffer (16-bit register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit register) TOP BOTTOM ATmega48/88/168 119.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit counter) = (16-bit comparator ) OCFnx (Int.req.) Waveform generator WGMn3:0 ...
Page 118
... Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin system reset occur, the OC1x Register is reset to “0”. 2545T–AVR–05/11 110. ATmega48/88/168 “Accessing 16-bit registers” Figure 16-5 on page 119 118 ...
Page 119
... The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Out- 2545T–AVR–05/11 Waveform generator I/O for details. See “Register description” on page 130. Table 16-1 on page ATmega48/88/168 OCnx PORT ...
Page 120
... The timing diagram for the CTC mode is shown in (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 2545T–AVR–05/11 ATmega48/88/168 118.) “Timer/counter timing diagrams” on page Figure 16-6 on page 127. ...
Page 121
... OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATmega48/88/168 OCnA interrupt flag set or ICFn interrupt flag set (interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 1 + 121 ...
Page 122
... The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location 2545T–AVR–05/11 ( TOP log R = ---------------------------------- - FPWM log ATmega48/88/168 ) Figure 16-7. The figure OCRnx/BOTTOM update and TOVn interrupt flag set and OCnA interrupt flag set or ICFn interrupt flag set (interrupt on TOP) (COMnx1 (COMnx1 ...
Page 123
... The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set 2545T–AVR–05/11 Table on page f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCR1A is set to zero (0x0000). This feature clk_I/O ATmega48/88/168 130). The actual OC1x ) 123 ...
Page 124
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg- ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This 2545T–AVR–05/11 ATmega48/88/168 ( ) TOP ...
Page 125
... The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and 2545T–AVR–05/11 f OCnxPCPWM and Figure 16-9 on page 126). ATmega48/88/168 Table on page f clk_I/O = --------------------------- - ⋅ ⋅ ...
Page 126
... R = ---------------------------------- - PFCPWM Figure 16-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega48/88/168 ( ) TOP + log OCnA interrupt flag set or ICFn interrupt flag set (interrupt on TOP) OCRnx/TOP update and ...
Page 127
... OCnxPFCPWM Figure 16-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATmega48/88/168 f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx + 2 OCRnx value ...
Page 128
... TOP in various modes. When using phase and clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx value (update at TOP) ATmega48/88/168 OCRnx OCRnx + 1 OCRnx value TOP BOTTOM TOP TOP - 1 New OCRnx value /8). clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 128 ...
Page 129
... I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx value (update at TOP) ATmega48/88/168 /8). clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx value 129 ...
Page 130
... COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast Compare output mode, fast PWM COM1A0/COM1B0 ATmega48/88/168 – – WGM11 R R shows the COM1x1:0 bit functionality when the ...
Page 131
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase correct PWM mode” on page 123. Table 16-4 on page ATmega48/88/168 Description Normal port operation, OC1A/OC1B disconnected. WGM13 11: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...
Page 132
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R ATmega48/88/168 Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICR1 BOTTOM OCR1A ...
Page 133
... External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – – R/W R ATmega48/88/168 128 – – – Figure 0 – TCCR1C R 0 133 ...
Page 134
... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See “Accessing 16-bit registers” on page 110. ATmega48/88/168 R/W R/W R/W R See “Accessing 16-bit R/W R/W R/W R R/W R/W R/W R TCNT1H ...
Page 135
... Initial value • Bit 7, 6 – Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, input capture interrupt enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled ...
Page 136
... Initial value • Bit 7, 6 – Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, input capture flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...
Page 137
... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk clk I/O Synchronization ATmega48/88/168 and “16-bit Timer/Counter1 with PWM” on page /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge detector ...
Page 138
... Figure 17-2. Prescaler for timer/counter0 and timer/counter1 PSRSYNC Note: 2545T–AVR–05/11 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O clk I/O T0 Synchronization T1 Synchronization clk 1. The synchronization logic on the input pins ( ATmega48/88/168 (1) . Clear T1 T1/T0) is shown in Figure 17-1 on page /2.5. clk_I/O clk T0 137. 138 ...
Page 139
... TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 2545T–AVR–05/ TSM – – – R ATmega48/88/168 – – PSRASY PSRSYNC R R R/W R GTCCR 139 ...
Page 140
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the The PRTIM2 bit in Timer/Counter2 module. Figure 18-1. 8-bit timer/counter block diagram. 2545T–AVR–05/11 “Pinout Atmel ATmega48/88/168.” on page “Register description” on page “Minimizing power consumption” on page 41 Count Clear Control logic ...
Page 141
... MCU clock, clk T2 152. shows a block diagram of the counter and its surrounding environment. ATmega48/88/168 for details. The compare match event will also 159. For details on clock sources and prescaler, see . When the AS2 I/O “ ...
Page 142
... Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 145. shows a block diagram of the Output Compare unit. ATmega48/88/168 TOVn (Int.req.) T/C clk Tn oscillator Prescaler top in the following ...
Page 143
... OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. 2545T–AVR–05/11 DATA BUS OCRnx = (8-bit comparator) top bottom Waveform generator FOCn WGMn1:0 ATmega48/88/168 TCNTn OCFnx (int.req.) OCnx COMnX1:0 143 ...
Page 144
... The design of the Output Compare pin logic allows initialization of the OC2x state before the out- put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. 2545T–AVR–05/11 Waveform generator clk I/O See “Register description” on page 153. ATmega48/88/168 Figure 18-4 shows a simplified OCnx 0 D ...
Page 145
... TCNT2 and OCR2A, and then coun- ter (TCNT2) is cleared. 2545T–AVR–05/11 Table 18-5 on page 154. For fast PWM mode, refer to Table 18-7 on page 144.). “Timer/counter timing diagrams” on page Figure 18-5 on page ATmega48/88/168 Table 18-6 on 155. 149. 146. The counter value 145 ...
Page 146
... OCnx ⋅ ⋅ OCRnx 1 + Flag is set in the same timer clock cycle that the TOV2 ATmega48/88/168 OCnx interrupt flag set (COMnx1 OC2A ) 146 = ...
Page 147
... Figure 18-6. The TCNT2 value is in the timing diagram shown as a his Table 18-3 on page f = OCnxPWM ATmega48/88/168 OCRnx interrupt flag set OCRnx update and TOVn interrupt flag set (COMnx1 (COMnx1 154). The actual OC2x value will only f clk_I/O ----------------- - ⋅ ...
Page 148
... OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM 2545T–AVR–05/11 18-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating TCNTn OCnx OCnx Period 1 ATmega48/88/168 = f /2 when OCR2A is set to zero. This fea- oc2 clk_I/O OCnx interrupt flag set OCRnx update TOVn interrupt flag set ...
Page 149
... OCnxPCPWM Figure 18-7 on page 148 contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega48/88/168 Table 18-4 on page 154). The actual OC2x f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low Figure 18-7 on page 148 ...
Page 150
... OCF2A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8). clk_I/O I/O Tn /8) I/O TOP - 1 TOP ATmega48/88/168 /8). clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx value BOTTOM BOTTOM + 1 TOP BOTTOM + 1 /8). clk_I/O OCRnx + 2 150 ...
Page 151
... The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin 2545T–AVR–05/11 Enable interrupts, if needed. ATmega48/88/168 151 ...
Page 152
... Timer/counter prescaler Figure 18-12. Prescaler for Timer/Counter2. PSRASY 2545T–AVR–05/11 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) clk I/O clk T2S Clear TOSC1 AS2 CS20 CS21 CS22 ATmega48/88/168 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 152 ...
Page 153
... Normal port operation, OC2A disconnected 1 Toggle OC2A on compare match 0 Clear OC2A on compare match 1 Set OC2A on compare match shows the COM2A1:0 bit functionality when the WGM21:0 bits are set ATmega48/88/168 . clk is by default connected to the main T2S T2S /8, clk /32, clk T2S T2S as well as 0 (stop) may be selected ...
Page 154
... COM2B1:0 bit functionality when the WGM22:0 bits Compare output mode, non-PWM mode. COM2B0 Description 0 Normal port operation, OC2B disconnected 1 Toggle OC2B on compare match 0 Clear OC2B on compare match 1 Set OC2B on compare match ATmega48/88/168 (1) . “Fast PWM mode” on page 146 (1) . “Phase correct PWM mode” on 154 ...
Page 155
... Note: • Bits 3, 2 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM21:0: Waveform generation mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting ...
Page 156
... MAX= 0xFF 2. BOTTOM= 0x00 FOC2A FOC2B – ATmega48/88/168 Timer/counter mode of Update of operation TOP OCRx at Normal 0xFF Immediate PWM, 0xFF TOP phase correct CTC OCRA Immediate Fast PWM 0xFF BOTTOM Reserved – – ...
Page 157
... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bit 3 – WGM22: Waveform generation mode See the description in the • Bit 2:0 – CS22:0: Clock select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 18-9 ...
Page 158
... – – – – ATmega48/88/168 R/W R/W R/W R – OCIE2B OCIE2A TOIE2 R R/W R/W R – OCF2B OCF2A ...
Page 159
... A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. 2545T–AVR–05/ – EXCLK AS2 TCN2UB OCR2AUB R R/W R ATmega48/88/168 OCR2BUB TCR2AUB TCR2BUB When AS2 is I/O 0 ASSR R 0 159 ...
Page 160
... TSM – – – R for a description of the Timer/Counter Synchronization mode. ATmega48/88/168 – – PSRASY PSRSYNC GTCCR R R R/W R “Bit 7 – TSM: Timer/counter syn- 160 ...
Page 161
... Double speed (CK/2) master SPI mode 19.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel ATmega48/88/168 and peripheral devices or between several AVR devices. The USART can also be used in Master SPI mode, PRSPI bit in module. 2545T–AVR–05/11 “ ...
Page 162
... Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission 2545T–AVR–05/11 (1) . DIVIDER /2/4/8/16/32/64/128 1. Refer to Figure 1-1 on page 2, and ATmega48/88/168 Table 14-3 on page 78 for SPI pin placement. Figure 19-2 on page 162 ...
Page 163
... Direction, master SPI User defined Input User defined User defined See “Alternate functions of port B” on page 78 tion of the user defined SPI pins. ATmega48/88/168 SHIFT ENABLE “Alternate port Direction, slave SPI Input User defined Input Input for a detailed description of how to define the direc- ...
Page 164
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See ”About code examples” on page 8. ATmega48/88/168 164 ...
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... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. See ”About code examples” on page 8. ATmega48/88/168 165 ...
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... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing below. 2545T–AVR–05/11 and Figure 19-4 on page 167. Data bits are shifted out and latched in on Table 19-3 on page 168 ATmega48/88/168 Figure and Table 19-4 on page 168, as done 166 ...
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... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega48/88/168 Trailing edge Setup (falling) Sample (falling) Setup (rising) Sample (rising) Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 3 Bit 4 Bit 5 Bit 6 ...
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... Figure 19-3 on page 167 and CPOL functionality. CPOL Leading edge 0 Rising 1 Falling Figure 19-3 on page 167 CPHA Functionality CPHA Leading edge 0 Sample 1 Setup ATmega48/88/168 CPOL CPHA SPR1 SPR0 R/W R/W R/W R Figure 19-4 on page 167 for an example. The Trailing edge Falling ...
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... SPI Data Register. • Bit 5..1 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bit 0 – SPI2X: Double SPI speed bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
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... SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 2545T–AVR–05/ MSB R/W R/W R/W R ATmega48/88/168 LSB R/W R/W R/W R SPDR Undefined 170 ...
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... Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. 2545T–AVR–05/11 ATmega48/88/168 see “USART in SPI mode” on page “Minimizing power consumption” on page 41 Table 20-1 on page 199 ...
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... UBRRn [H:L] BAUD RATE GENERATOR UDRn (transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDRn (receive) UCSRnA 1. Refer to Figure 1-1 on page 2 and shows a block diagram of the clock generation logic. ATmega48/88/168 Clock generator OSC SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL ...
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... Receiver base clock (internal signal). clk Input from XCK pin (internal signal). Used for synchronous slave cki operation. Clock output to XCK pin (internal signal). Used for synchronous master cko operation. System clock frequency. ATmega48/88/168 U2Xn / DDR_XCKn 0 1 Figure 20-2 ...
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... BAUD BAUD BAUD 1. The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) System clock frequency Contents of the UBRRnH and UBRRnL registers, (0-4095) ATmega48/88/168 Equation for Equation for (1) calculating UBRRn value f OSC ...
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... Figure 20-2 on page 173 depends on the stability of the system clock source therefore recommended to osc UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 20-3 shows, when UCPOLn is zero the data will be changed at ATmega48/88/168 for details. f OSC < f ---------- - XCK 4 Sample Sample 175 ...
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... even n 1 – ⊕ odd n 1 – Parity bit using even parity even Parity bit using odd parity odd Data bit n of the character n ATmega48/88/168 FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
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... The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. 2545T–AVR–05/11 ATmega48/88/168 177 ...
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... UCSRnC,r16 ret (1) USART_Init(MYUBRR) /*Set baud rate */ UBRR0H = (unsigned char)(ubrr>>8); UBRR0L = (unsigned char)ubrr; Enable receiver and transmitter */ UCSR0B = (1<<RXEN0)|(1<<TXEN0); /* Set frame format: 8data, 2stop bit */ UCSR0C = (1<<USBS0)|(3<<UCSZ00); 1. See ”About code examples” on page 8. ATmega48/88/168 178 ...
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... UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDRn,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; 1. See ”About code examples” on page 8. ATmega48/88/168 179 ...
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... Put data into buffer, sends the data */ UDRn = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization. 2. See ”About code examples” on page 8. ATmega48/88/168 180 ...
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... When the first stop bit is received, that is, a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. 2545T–AVR–05/11 ATmega48/88/168 181 ...
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... UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret (1) /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See ”About code examples” on page 8. ATmega48/88/168 182 ...
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... See ”About code examples” on page 8. The receive function example reads all the I/O registers into the register file before any compu- tation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. ATmega48/88/168 183 ...
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... The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. 2545T–AVR–05/11 “Parity bit calculation” on page 176 ATmega48/88/168 and “Parity checker” on page 184. 184 ...
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... UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See ”About code examples” on page 8. illustrates the sampling process of the start bit of an incoming frame. The sample ATmega48/88/168 Figure 20-5 185 ...
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... RxD Sample (U2X = Sample (U2X = shows the sampling of the stop bit and the earliest possible beginning ATmega48/88/168 START Figure 20-6 shows the sampling of the data bits and ...
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... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 20-3 on page 188 ATmega48/88/168 STOP 1 (A) ( ...
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... Recommended maximum receiver baud rate error for double speed mode (U2Xn = 1 (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104,35 8 96.00 103.90 9 96.39 103.53 10 96.70 103.23 ATmega48/88/168 Recommended max. Max. total error (%) receiver error (%) +6.67/-6.8 ±3.0 +5.79/-5.88 ±2.5 +5.11/-5.19 ±2.0 +4.58/-4.54 ±2.0 +4.14/-4.19 ±1.5 +3.78/-3.83 ±1.5 Recommended max. Max. total error (%) receiver error (%) +5.66/-5.88 ±2.5 +4.92/-5.08 ±2.0 +4.35/-4.48 ±1.5 +3.90/-4.00 ±1.5 +3.53/-3.61 ± ...
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... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 2545T–AVR–05/11 ATmega48/88/168 189 ...
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... Data Register Empty interrupt (see description of the UDRIEn bit). 2545T–AVR–05/ RXB[7:0] TXB[7:0] R/W R/W R/W R RXCn TXCn UDREn FEn R R ATmega48/88/168 R/W R/W R/W R DORn UPEn U2Xn MPCMn R R R/W R UDRn (Read) UDRn (Write) UCSRnA ...
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... TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. 2545T–AVR–05/11 “Multi-processor communication mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega48/88/168 188 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 191 ...
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... UMSELn1 UMSELn0 UPMn1 R/W R/W R UMSELn bits settings. UMSELn0 See “USART in SPI mode” on page 199 operation. ATmega48/88/168 UPMn0 USBSn UCSZn1 UCSZn0 R/W R/W R/W R Table 20-4. Mode Asynchronous USART Synchronous USART (Reserved) (1) Master SPI (MSPIM) ...
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... USBS bit settings. USBSn 0 1 UCSZn bits settings. UCSZn1 ATmega48/88/168 Parity mode Disabled Reserved Enabled, even parity Enabled, odd parity Stop bit(s) 1-bit 2-bit UCSZn0 Character size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 ...
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... R/W R/W R/W R 187). The error values are calculated using the following BaudRate ⎛ Closest Match Error[%] = ------------------------------------------------- - 1 ⎝ BaudRate ATmega48/88/168 Received data sampled (input on RxDn pin) Falling XCKn edge Rising XCKn edge UBRRn[11: R/W R/W R/W R/W R/W R/W R/W R ...
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... U2Xn = 1 U2Xn = 0 Error UBRRn Error 0.2% 47 0.0% 0.2% 23 0.0% 0.2% 11 0.0% -3.5% 7 0.0% -7.0% 5 0.0% 8.5% 3 0.0% 8.5% 2 0.0% 8.5% 1 0.0% -18.6% 1 -25.0% 8.5% 0 0.0% – – – – – – 125Kbps 115.2Kbps ATmega48/88/168 f = 2.0000MHz osc U2Xn = 1 U2Xn = 0 UBRRn Error UBRRn Error 95 0.0% 51 0.2% 47 0.0% 25 0.2% 23 0.0% 12 0.2% 15 0.0% 8 -3.5% 11 0.0% 6 -7.0% 7 0.0% 3 8.5% 5 0.0% 2 8.5% 3 0.0% 1 8.5% 2 0.0% 1 -18.6% 1 ...
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... ATmega48/88/168 f = 7.3728MHz osc U2Xn = 0 U2Xn = 1 Error UBRRn Error UBRRn 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0.0% 63 0.2% 23 0.0% 47 2.1% 15 0.0% 31 0.2% 11 0.0% 23 -3.5% 7 0.0% 15 -7.0% 5 0.0% 11 8.5% 3 0.0% 7 8.5% 1 0.0% 3 ...
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... U2Xn = 0 Error UBRRn Error UBRRn -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – 1Mbps 691.2Kbps ATmega48/88/168 f = 14.7456MHz osc U2Xn = 1 U2Xn = 0 Error UBRRn Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0.0% 95 0.0% 63 0.0% 71 0.0% 47 0.0% 47 0.0% 31 0.0% 35 0.0% 23 0.0% 23 0.0% 15 0.0% 17 0.0% 11 0.0% 11 0.0% 7 0. ...
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... U2Xn = 0 Error UBRRn Error UBRRn 0.0% 479 0.0% -0.1% 239 0.0% 0.2% 119 0.0% -0.1% 79 0.0% 0.2% 59 0.0% 0.6% 39 0.0% 0.2% 29 0.0% -0.8% 19 0.0% 0.2% 14 0.0% 2.1% 9 0.0% -3.5% 4 0.0% 0.0% 4 -7.8% 0.0% – – 0.0% – – 2Mbps 1.152Mbps ATmega48/88/168 f = 20.0000MHz osc U2Xn = 1 U2Xn = 0 Error UBRRn Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0.0% 86 -0.2% 119 0.0% 64 0.2% 79 0.0% 42 0.9% 59 0.0% 32 -1.4% 39 0.0% 21 -1.4% 29 0.0% 15 1.7% 19 0.0% 10 -1. ...
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... USART in MSPIM is enabled (that is, TXENn and RXENn bit set to one). The internal clock generation used in MSPIM mode is identical to the USART synchronous mas- ter mode. The baud rate or UBRRn setting can therefore be calculated using the same equations, see 2545T–AVR–05/11 Table 21-1 on page 200: ATmega48/88/168 199 ...
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... Data bits are shifted out and latched in on opposite edges of UCPOLn and UCPHAn functionality. UCPHAn SPI mode ATmega48/88/168 Equation for calculating UBRRn (1) f OSC UBRRn ( ) + 1 Table 21-2. Note that changing the setting of any of Leading edge Trailing edge Sample (rising) Setup (falling) ...