ATmega48 Automotive Atmel Corporation, ATmega48 Automotive Datasheet - Page 58

• Manufacturer Part Number: ATmega48 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega48 Automotive

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 256
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.2.2
12.2.3
12.2.4
58
Atmel ATtiny24/44/84 [Preliminary]
Toggling the Pin
Switching Between Input and Output
Reading the Pin Value
If PORTxn is written logical one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logical zero when the pin is configured as an output pin,
the port pin is driven low (zero).
Writing a logical one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01)
or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully
acceptable, as a high-impedance environment will not notice the difference between a strong
high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR register can be set
to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn,
PORTxn} = 0b10) as an intermediate step.
Table 12-1 on page 58
Table 12-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
on page 59
pin value. The maximum and minimum propagation delays are denoted t
respectively.
DDxn
0
0
0
1
1
PORTxn
shows a timing diagram of the synchronization when reading an externally applied
0
1
1
0
1
Port Pin Configurations
(in MCUCR)
summarizes the control signals for the pin value.
PUD
X
0
1
X
X
Figure 12-2 on page
Output
Output
Input
Input
Input
I/O
Pull-up
Yes
No
No
No
No
57, the PINxn Register bit and the pre-
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
pd,max
7701E–AVR–02/11
Figure 12-3
and t
pd,min