ATmega48PA Atmel Corporation, ATmega48PA Datasheet - Page 141

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ATmega48PA

Manufacturer Part Number
ATmega48PA
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega48PA

Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
256
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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16.11.8
16.11.9
8271D–AVR–05/11
TIMSK1 – Timer/Counter1 Interrupt Mask Register
TIFR1 – Timer/Counter1 Interrupt Flag Register
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See
• Bit 7, 6 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read
as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 59) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read
as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF1B Flag, located in
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 59) is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See
• Bit 7, 6 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read
as zero.
Bit
(0x6F)
Read/Write
Initial Value
Bit
0x16 (0x36)
Read/Write
Initial Value
”Interrupts” on page
”Accessing 16-bit Registers” on page
R
R
7
0
7
0
ATmega48A/PA/88A/PA/168A/PA/328/P
59) is executed when the TOV1 Flag, located in TIFR1, is set.
R
R
6
0
6
0
ICIE1
R/W
ICF1
R/W
5
0
5
0
R
4
0
R
4
0
117.
R
3
0
R
3
0
OCIE1B
OCF1B
R/W
R/W
2
0
2
0
OCIE1A
OCF1A
R/W
R/W
1
0
1
0
TOIE1
TOV1
R/W
R/W
0
0
0
0
TIMSK1
TIFR1
141

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