ATmega640 Atmel Corporation, ATmega640 Datasheet
ATmega640
Specifications of ATmega640
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ATmega640 Summary of contents
Page 1
... Six/Twelve PWM Channels with Programmable Resolution from Bits (ATmega1281/2561, ATmega640/1280/2560) – Output Compare Modulator – 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560) – Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560) – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – ...
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... Pin Configurations Figure 1-1. TQFP-pinout ATmega640/1280/2560 100 (OC0B) PG5 1 (RXD0/PCINT8) PE0 2 (TXD0) PE1 3 (XCK0/AIN0) PE2 4 (OC3A/AIN1) PE3 5 (OC3B/INT4) PE4 6 (OC3C/INT5) PE5 7 (T3/INT6) PE6 8 (CLKO/ICP3/INT7) PE7 9 VCC 10 GND 11 (RXD2) PH0 12 (TXD2) PH1 ...
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... Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view Table 1- Note: 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 CBGA-pinout ATmega640/1280/2560 GND AREF PF0 PF2 AVCC PG5 PF1 PF3 PE2 PE0 PE1 ...
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... PB6 Note: 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 INDEX CORNER The large center pad underneath the QFN/MLF package is made of metal and internally con- nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. ...
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... Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and sys debugger/simulators, in-circuit emulators, and evaluation kits. 2549NS– ...
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... Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1. Configuration Summary Device Flash EEPROM ATmega640 64KB ATmega1280 128KB ATmega1281 128KB ATmega2560 256KB ATmega2561 256KB 2.3 Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. ...
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... The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on 2.3.6 Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability ...
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... As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port L also serves the functions of various special features of the ATmega640/1280/2560 as listed on 2.3.14 RESET Reset input ...
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... AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con- nected to V through a low-pass filter. 2.3.18 AREF This is the analog reference pin for the A/D Converter. 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 , even if the ADC is not used. If the ADC is used, it should be connected ...
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... The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 ® ® QTouch Library provides a simple to use solution to realize touch sensitive inter- ® ...
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... DDRK DDK7 (0x106) PINK PINK7 (0x105) PORTJ PORTJ7 (0x104) DDRJ DDJ7 (0x103) PINJ PINJ7 (0x102) PORTH PORTH7 (0x101) DDRH DDH7 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Bit 6 Bit 5 Bit 4 Bit USART3 I/O Data Register - - - USART3 Baud Rate Register Low Byte - - - UMSEL30 UPM31 UPM30 ...
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... Reserved - (0xC6) UDR0 (0xC5) UBRR0H - (0xC4) UBRR0L (0xC3) Reserved - (0xC2) UCSR0C UMSEL01 (0xC1) UCSR0B RXCIE0 (0xC0) UCSR0A RXC0 (0xBF) Reserved - 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Bit 6 Bit 5 Bit 4 Bit 3 PINH6 PINH5 PINH4 PINH3 - - - - - - - - - - - - - - - - - ...
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... TCCR1C FOC1A (0x81) TCCR1B ICNC1 (0x80) TCCR1A COM1A1 (0x7F) DIDR1 - (0x7E) DIDR0 ADC7D (0x7D) DIDR2 ADC15D 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Bit 6 Bit 5 Bit 4 Bit TWAM5 TWAM4 TWAM3 TWAM2 TWEA TWSTA TWSTO TWWC 2-wire Serial Interface Data Register TWA5 TWA4 TWA3 ...
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... EEDR 0x1F (0x3F) EECR - 0x1E (0x3E) GPIOR0 0x1D (0x3D) EIMSK INT7 0x1C (0x3C) EIFR INTF7 0x1B (0x3B) PCIFR - 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Bit 6 Bit 5 Bit 4 Bit 3 REFS0 ADLAR MUX4 MUX3 ACME - - MUX5 ADSC ADATE ADIF ADIE ADC Data Register High byte ...
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... When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis- ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 2549NS– ...
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... BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Description Rd ← ← Rdh:Rdl ← Rdh:Rdl + K Rd ← ← ← ← Rdh:Rdl ← Rdh:Rdl - K Rd ← ...
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... Load Program Memory and Post-Inc ELPM Extended Load Program Memory ELPM Rd, Z Extended Load Program Memory 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Description then PC ← then PC ← then PC ← then PC ← I/O(P,b) ← 1 I/O(P,b) ← ...
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... NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break Note: 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Description EICALL and EIJMP do not exist in ATmega640/1280/1281. ELPM does not exist in ATmega640. Operation Flags Rd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1 None (Z) ← R1:R0 None Rd ← P None P ← Rr None STACK ← Rr None Rd ← ...
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... Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 100C1 100-ball, Chip Ball Grid Array (CBGA) 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Ordering Code ATmega640V-8AU (4) ATmega640V-8AUR ATmega640V-8CU (4) ATmega640V-8CUR ATmega640-16AU (4) ATmega640-16AUR ATmega640-16CU (4) ATmega640-16CUR Package Type (1)(3) Package Operation Range 100A 100A 100C1 100C1 Industrial (-40° ...
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... Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 4. Tape & Reel 100A 100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 100C1 100-ball, Chip Ball Grid Array (CBGA) 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Ordering Code ATmega1280V-8AU (4) ATmega1280V-8AUR ATmega1280V-8CU (4) ATmega1280V-8CUR ...
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... Halide free and fully Green. 4. Tape & Reel 64A 64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M2 64-pad, 9mm × 9mm × 1.0mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Ordering Code ATmega1281V-8AU (4) ATmega1281V-8AUR ATmega1281V-8MU (4) ...
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... Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 4. Tape & Reel 100A 100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 100C1 100-ball, Chip Ball Grid Array (CBGA) 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Ordering Code ATmega2560V-8AU (4) ATmega2560V-8AUR ATmega2560V-8CU (4) ATmega2560V-8CUR ...
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... Halide free and fully Green. 4. Tape & Reel 64A 64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M2 64-pad, 9mm × 9mm × 1.0mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Ordering Code ATmega1281V-8AU (4) ATmega1281V-8AUR ATmega1281V-8MU (4) ...
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... Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 B PIN 1 IDENTIFIER TITLE 100A, 100-lead Body Size, 1 ...
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... TYP 0.90 TYP 2325 Orchard Parkway San Jose, CA 95131 R 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 E Marked A1 Identifier TOP VIEW Øb A1 Corner BOTTOM VIEW TITLE 100C1, 100-ball 1.2 mm Body, Ball Pitch 0.80 mm Chip Array BGA Package (CBGA) ...
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... Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 B PIN 1 IDENTIFIER ...
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... TOP VIEW BOTTOM VIEW Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2325 Orchard Parkway San Jose, CA 95131 R 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 D E Pin #1 Corner Pin #1 1 Option A Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) ...
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... Errata 11.1 ATmega640 rev. B • Inaccurate ADC conversion in differential mode with 200× gain • High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200× gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None ...
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... If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 30 ...
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... If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled. 11.11 ATmega2560 rev. B Not sampled. 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 31 ...
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... In some cases this will cause a problem, for example reading SREG it will appear that the I-flag is cleared writing to the PIN registers, the port will toggle twice reading registers with interrupt flags, the flags will appear to be cleared. 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 32 ...
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... Incorrect ADC reading in differential mode • Internal ADC reference has too low value • IN/OUT instructions may be executed twice when Stack is in external RAM • EEPROM read from application code does not work in Lock Bit Mode 3 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 33 ...
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... Use internal RAM for stack pointer. 6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 34 ...
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... Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 35 ...
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... Rev. 2549L-08/ 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Added Atmel QTouch Library Support and QTouch Sensing Capablity Features Updated Cross-reference in “Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler and 0” on page 68 Updated Assembly codes in section “USART Initialization” on page 210 Added “Standard Power-On Reset” on page Added “ ...
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... Rev. 2549H-06/ 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Updated “SPI Timing Characteristics” on page Updated “ADC Characteristics – Preliminary Data” on page Updated ordering code in “ATmega640” on page Updated Table 1-1 on page 3. Updated “Pin Descriptions” on page 7. Updated “Stack Pointer” on page 16. Updated “ ...
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... Rev. 2549D-12/ 10. 11. 12. 13. 14. 2549NS–AVR–05/11 ATmega640/1280/1281/2560/2561 Updated “Features” on page 1. Added Figure 1-2 on page 3, Table 1-1 on page Updated “” on page 46. Updated “Power Management and Sleep Modes” on page Updated note for Table 12-1 on page Updated Figure 26-9 on page 285 ...
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... V ” on page CC Updated “Ordering Information” on page Updated “Packaging Information” on page Updated “Errata” on page 29. JTAG ID/Signature for ATmega640 updated: 0x9608. Updated Table 13-7 on page 81. Updated “Serial Programming Instruction set” on page Updated “Errata” on page 29. Initial version. ...
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