ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet
ATmega64M1
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ATmega64M1 Summary of contents
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... On-chip PLL for fast PWM ( 32MHz, 64MHz) and CPU (16MHz) • Operating Voltage: 2.7V - 5.5V • Extended Operating Temperature: – -40°C to +85°C • Core Speed Grade: – 8MHz @ 2.7 - 4.5V – 16MHz @ 4.5 - 5.5V ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash ATmega16M1 ATmega32M1 ATmega64M1 Preliminary 8209D–AVR–11/10 ...
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Pin Configurations Figure 1-1. ATmega16M1/32M1/64M1 TQFP32/QFN32 (7 × 7 mm) Package. (PCINT18/PSCIN2/OC1A/MISO_A) PD2 (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 (PCINT9/PSCIN1/OC1B/SS_A) PC1 (PCINT10/T0/TXCAN) PC2 (PCINT11/T1/RXCAN/ICP1B) PC3 (PCINT0/MISO/PSCOUT2A) PB0 ATmega16M1/32M1/64M1 VCC 4 GND PB4 (AMP0+/PCINT4) 23 ...
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Pin Descriptions Table 1-1. QFN32 Pin Number 8209D–AVR–11/10 ATmega16M1/32M1/64M1 Pinout description Mnemonic Type GND Power Ground: 0V reference AGND Power Analog Ground: 0V reference for ...
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Table 1-1. QFN32 Pin Number ATmega16M1/32M1/64M1 4 Pinout description (Continued) Mnemonic Type PSCIN1 (PSC Digital Input 1) OC1B (Timer 1 Output Compare B) PC1 I/O SS_A (Alternate SPI Slave ...
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Table 1-1. QFN32 Pin Number Note: 2. Overview The ATmega16M1/32M1/64M1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ...
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Block Diagram Figure 2-1. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in ...
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The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to continue functioning. The Power-down mode saves the regis- ter contents but freezes the Oscillator, disabling all other chip functions until the ...
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Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D ...
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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be ...
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AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look ...
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The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 6.3.1 SREG – AVR Status Register Bit Read/Write Initial Value • Bit 7 – I: ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Figure 6-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 6.5 Stack Pointer The Stack is mainly used for storing ...
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SPH and SPL – Stack Pointer High and Stack Pointer Low Register Bit Read/Write Initial Value 6.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU ...
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Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be ...
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Assembly Code Example in r16, SREG cli sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 C Code Example char cSREG; cSREG = SREG; /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ ...
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Memories 7.1 Overview This section describes the different memories in the ATmega16M1/32M1/64M1. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16M1/32M1/64M1 features an EEPROM Memory for data ...
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SRAM Data Memory Figure 7-2 The ATmega16M1/32M1/64M1 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from ...
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Figure 7-3. 7.4 EEPROM Data Memory The ATmega16M1/32M1/64M1 contains 512B/1K/2K bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...
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Preventing EEPROM Corruption During periods of low V too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. ...
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Register Description 7.7.1 EEARH and EEARL – The EEPROM Address Registers Bit Read/Write Initial Value • Bits 15:10 – Res: Reserved These bits are reserved and will always read as zero. • Bits 9:0 – EEAR[8:0]: EEPROM Address The ...
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While EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 7-1. EEPM1 • Bit 3 – EERIE: EEPROM ...
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When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write (unsigned int uiAddress, unsigned char ucData 8209D–AVR–11/10 ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...
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System Clock and their Distribution 8.1 Clock Systems and their Distribution Figure 8-1 need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep ...
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PLL Clock – clk PLL The PLL clock allows the fast peripherals to be clocked directly from a 64/32MHz clock. A 16MHz clock is also derived for the CPU. 8.1.5 ADC Clock – clk ADC The ADC is provided ...
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Table 8-2. Typ Time-out (V 8.3 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial ...
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Table 8-3. CKSEL3..1 100 101 110 111 Notes: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 8-4. Table 8-4. CKSEL0 Notes: 8.5 Calibrated Internal RC ...
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This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 8-1 on page hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy ...
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Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1 MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only when the PLLE bit in the ...
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External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 8-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 8-4. Table 8-8. ...
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System Clock Prescaler The ATmega16M1/32M1/64M1 system clock can be divided by setting the Clock Prescale Reg- ister – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be ...
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The CAL6:0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. 8.11.2 PLLCSR – PLL ...
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Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure ...
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Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to ...
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Idle mode. If the ADC is enabled, a conversion starts automati- cally when this mode is entered. 9.4 ADC Noise Reduction Mode When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU ...
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Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. 9.8 Minimizing Power Consumption There are several issues to consider when trying ...
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I/O clock (clk be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to ...
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Bit 1 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it ...
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System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 10-1. Reset Logic 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to trigger the ...
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Figure 10-3. MCU Start-up, RESET Extended Externally 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is not running. ...
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Figure 10-5. Brown-out Reset During Operation 10.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out ...
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Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC or the DAC, the user must always allow the reference to start up before the output from the Analog Compar- ator or ADC or ...
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The “Watchdog Timer Always On” (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Inter- rupt mode bit (WDIE) are locked to 1 and 0 ...
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Assembly Code Example WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in andi out ; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out ...
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Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching ...
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Register Description 10.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit Read/Write Initial Value • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if ...
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System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed ...
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Table 10-2. WDP3 ATmega16M1/32M1/64M1 52 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 (2048) cycles 0 ...
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Interrupts ...
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Table 11-1. Vector No Notes: Table 11-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2 Kbytes and the ...
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When the BOOTRST Fuse is programmed and the Boot section size set to 2 Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16M1/32M1/64M1 is: Address Labels Code .org 0x002 0x002 0x004 ... ...
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Register Description 11.2.1 MCUCR – MCU Control Register Bit Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. ...
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Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret C Code Example void Move_interrupts(void Enable change of ...
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External Interrupts The External Interrupts are triggered by the INT3:0 pins or any of the PCINT23:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT23:0 pins are configured as outputs. This feature provides ...
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Register Description 12.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit Read/Write Initial Value • Bit 7:0 – ISC3[1:0] - ISC0[1:0]: Interrupt Sense Control 3 to ...
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EIFR – External Interrupt Flag Register Bit Read/Write Initial Value • Bit 7:4 – Res: Reserved These bits are reserved and will always read as zero. • Bit 3:0 – INTF[3:0]: External Interrupt Flag 3:0 When an edge or ...
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PCIFR – Pin Change Interrupt Flag Register Bit Read/Write Initial Value • Bit 7:4 - Res: Reserved These bits are reserved and will always read as zero. • Bit 3 - PCIF3: Pin Change Interrupt Flag 3 When a ...
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PCMSK2 – Pin Change Mask Register 2 Bit Read/Write Initial Value • Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16 Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set ...
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I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 13-2. General Digital I/O Note: 13.2.1 Configuring the Pin Each port pin consists ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 13-3. Synchronization when Reading an Externally Applied Pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock ...
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Assembly Code Example ... ; Define pull-ups and set outputs high ...
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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be present in all ...
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Table 13-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...
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Table 13-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • ADC4/PSCOUT0B/SCK/PCINT7 – Bit 7 PSCOUT0B, Output 0B of PSC. ADC4, Analog to Digital Converter, input channel 4. SCK, Master Clock ...
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ADC6/INT2/ACMPN1/AMP2-/PCINT5 – Bit 5 ADC6, Analog to Digital Converter, input channel 6. INT2, External Interrupt source 2. This pin can serve as an External Interrupt source to the MCU. ACMPN1, Analog Comparator 1 Negative Input. Configure the port pin ...
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Table 13-4 shown in Table 13-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8209D–AVR–11/10 and Table 13-5 relates the alternate functions ...
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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 13-6. Note: The alternate pin configuration is as follows: • D2A/AMP2+/PCINT15 – Bit 7 D2A, Digital to Analog output. AMP2+, Analog Differential Amplifier ...
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ADC10/ACMP1/PCINT14 – Bit 6 ADC10, Analog to Digital Converter, input channel 10. ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with ...
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SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDD0 slave, the SPI is activated when this pin is driven low. When ...
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Table 13-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8209D–AVR–11/10 ATmega16M1/32M1/64M1 Overriding Signals for Alternate Functions in PC3..PC0 PC3/T1/RXCAN/ PC2/T0/TXCAN/ ICP1B/PCINT11 PCINT10 PC1/PSCIN1/ PC0/INT3/ OC1B/SS_A/ PSCOUT1A/ PCINT9 ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-9. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • ACMP0/PCINT23 – Bit 7 ...
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ACMPN2, Analog Comparator 2 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Ana- log Comparator. INT0, External Interrupt source 0. This ...
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PCINT18/PSCIN2/OC1A/MISO_A, Bit 2 PCSIN2, PSC Digital Input 2. OC1A, Output Compare Match A output: This pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD2 set ...
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Table 13-11. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 13.3.4 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-12. Port ...
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The alternate pin configuration is as follows: • PCINT26/XTAL2/ADC0 – Bit 2 XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be ...
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Register Description 13.4.1 MCUCR – MCU Control Register Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and ...
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PORTD – Port D Data Register Bit Read/Write Initial Value 13.4.9 DDRD – Port D Data Direction Register Bit Read/Write Initial Value 13.4.10 PIND – Port D Input Pins Address Bit Read/Write Initial Value 13.4.11 PORTE – Port E ...
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Timer/Counter0 with PWM 14.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...
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Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case ...
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Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 14-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- pare (FOC0x) strobe bits in ...
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PWM refer to A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be ...
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Figure 14-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 14-6. Fast PWM Mode, ...
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OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 14.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...
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OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (see visible on the port pin if the data direction for the port pin is ...
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Figure 14-9 Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 14-10 mode and PWM mode, where OCR0A is TOP. Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn ...
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Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 ...
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Table 14-4 rect PWM mode. Table 14-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...
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Table 14-7 rect PWM mode. Table 14-7. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined ...
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TCCR0B – Timer/Counter Control Register B Bit Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...
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Table 14-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of ...
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Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt ...
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Timer/Counter1 with PWM 15.1 Features • True 16-bit Design (that is, allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Retriggering ...
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Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in ...
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The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of ...
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Table 15-2. Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the ...
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The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. Table 15-3. Assembly Code Example TIM16_ReadTCNTn: ; Save ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle. Table 15-4. Assembly Code Example TIM16_WriteTCNTn: C Code ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM RTG The 16-bit counter is ...
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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written ...
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I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 15.6.4 Using the Input Capture Unit as TCNT1 Retrigger ...
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The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...
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Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx ...
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PWM refer to page 124. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. ...
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Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define ...
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The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn ...
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When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next ...
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OCRnA set to MAX). The PWM reso- lution in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter ...
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TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period ...
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In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and ...
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PWM output can be generated by setting the COMnx1:0 to three (see page 124). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output ...
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Figure 15-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 15-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced ...
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Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 15.11 Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A Bit Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – ...
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Table 15-6 PWM mode. Table 15-6. COMnA1/COMnB1 Note: Table 15-7 correct or the phase and frequency correct, PWM mode. Table 15-7. COMnA1/COMnB1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB ...
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Table 15-8. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...
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When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – RTGEN ...
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A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 15.11.4 TCNT1H and TCNT1L – Timer/Counter1 ...
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ICR1H and ICR1L – Input Capture Register 1 Bit Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for ...
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TIFR1 – Timer/Counter1 Interrupt Flag Register Bit Read/Write Initial Value • Bit 7, 6 – Res: Reserved These bits are reserved and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is ...
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Timer/Counter0 and Timer/Counter1 Prescalers The “8-bit Timer/Counter0 with PWM” (see page prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the ...
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Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...
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Register Description 16.4.1 GTCCR – General Timer/Counter Control Register Bit Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is ...
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PSC – Power Stage Controller 17.1 Features • PWM waveform generation function with 6 complementary programmable outputs (able to control 3 half-bridges) • Programmable dead time control • PWM bit resolution • PWM clock frequency up ...
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PSC Description Figure 17-1. Power Stage Controller Block Diagram ATmega16M1/32M1/64M1 134 PSC Counter POCR_RB = Waveform Generator B POCR0SB = Overlap Protection POCR0RA = Waveform Generator A = POCR0SA Waveform Generator B POCR1SB = Overlap Protection POCR1RA = Waveform ...
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The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter is able to count top value determined by the contents of POCR_RB register and then according to the selected running mode, ...
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Figure 17-3. Cycle Presentation in Centered Mode PSC Counter Value Figure 17-2 on page 135 ter. Centered Mode is like One Ramp Mode which counts down and then up. Notice that the update of the waveform generator registers is done ...
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Figure 17-4. PSCOUTnA & PSCOUTnB Basic Waveforms in One Ramp mode PSC Counter PSCOUTnA PSCOUTnB On-Time A = (POCRnRAH/L - POCRnSAH/L) × 1/Fclkpsc On-Time B = (POCRnRBH/L - POCRnSBH/L) × 1/Fclkpsc Dead-Time A = (POCRnSAH × 1/Fclkpsc Dead-Time ...
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Center Aligned Mode In center aligned mode, the center of PSCOUTnA and PSCOUTnB signals are centered. Figure 17-6. PSCOUTnA & PSCOUTnB Basic Waveforms in Center Aligned Mode POCRnRB POCRnSB POCRnSA PSCOUTnA PSCOUTnB On-Time × POCRnSAH/L × ...
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Figure 17-7. Controlled Start and Stop Mechanism in Centered Mode POCRnRB POCRnSB POCRnSA PSC Counter Run PSCOUTnA PSCOUTnB Note: See “PCTL – PSC Control Register” on page 17.6 Update of Values To avoid unasynchronous and incoherent values in a cycle, ...
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Overlap Protection Thanks to Overlap Protection two outputs on a same module cannot be active at the same time cannot generate cross conduction. This feature can be disactivated thanks to POVEn (PSC Overlap Enable). 17.8 Signal Description ...
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Input Description Table 17-1. Name POCR_RB[11:0] POCRnSB[11:0] POCRnRA[11:0] POCRnSA[11:0] CLK I/O CLK PLL AC0O AC1O AC2O Table 17-2. Name PSCIN0 PSCIN1 PSCIN2 17.8.2 Output Description Table 17-3. Name PSCOUT0A PSCOUT0B PSCOUT1A PSCOUT1B PSCOUT2A PSCOUT2B Table 17-4. Name IRQPSCn PSCASY ...
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PSC Input For detailed information on the PSC, please refer to Application Note ‘AVR138: PSC Cookbook’, available on the Atmel web site. Each module 0, 1 and 2 of PSC has its own system to take into account one ...
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Figure 17-11. PSC Input Filtering 17.9.1.2 Signal Polarity One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit description in Section "PMICn – PSC Module n Input Control Register", page 150. If PELEVnx ...
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PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing Figure 17-12. PSC behaviour versus PSCn Input in Mode 001b to 10xb DT0 OT0 PSCOUTnA PSCOUTnB PSCn Input Figure 17-13. PSC behaviour versus PSCn Input A or Input ...
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Analog Synchronization Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation is mandatory for measurements. This signal can be selected between all falling or rising edge of PSCOUTnA or PSCOUTnB outputs. In center aligned ...
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Table 17-6. PCLKSELn 17.15 Interrupts ...
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When this bit is set, I/O pin affected to PSCOUT2B is connected to the PSC module 2 waveform generator B output and is set and clear according to the PSC operation. • Bit 4 – POEN2A: PSC Output 2A Enable ...
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Bit 1:0 – PSYNC0[1:0]: Synchronization Out for ADC Selection Select the polarity and signal source for generating a signal which will be sent from module 0 to the ADC for synchronization. Table 17-8. PSYNCn1 Table ...
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POCRnRBH and POCRnRBL – PSC Output Compare RB Register Bit Read/Write Initial Value Note according to module number The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously ...
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Bit 1:0 – Res: Reserved These bits are reserved and will always read as zero. 17.16.8 PCTL – PSC Control Register Bit Read/Write Initial Value • Bit 7:6 – PPRE1:0: PSC Prescaler Select This two bits select the PSC ...
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Bit 6 – PISELn: PSC Module n Input Select Clear this bit to select PSCINn as module n input. Set this bit to select Comparator n output as module n input. • Bit 5 – PELEVn: PSC Module n ...
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Bit 2 – PEVE1: PSC External Event 1 Interrupt Enable When this bit is set, an external event which can generates a fault on module 1 generates also an interrupt. • Bit 1 – PEVE: PSC External Event 0 ...
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SPI – Serial Peripheral Interface 18.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 18-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...
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Table 18-2. Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ; Enable SPI, Master, set clock rate fck/16 ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for ...
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Table 18-3. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8209D–AVR–11/10 (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret ...
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SS Pin Functionality 18.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Figure 18-3. SPI Transfer Format with CPHA = 0 Figure 18-4. SPI Transfer Format with CPHA = 1 18.5 Register Description 18.5.1 MCUCR – MCU Control Register Bit Read/Write Initial Value Bit 7– SPIPS: SPI Pin Redirection. Thanks to SPIPS ...
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SPCR – SPI Control Register Bit Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the ...
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Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...
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SPDR – SPI Data Register Bit Read/Write Initial Value • Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to ...
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CAN – Controller Area Network 19.1 Features • Full CAN Controller • Fully Compliant with CAN Standard rev 2.0 A and rev 2.0 B • 6 MOb (Message Object) with their own: – 11 bits of Identifier Tag (rev ...
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Message Formats The CAN protocol supports two message frame formats, the only essential difference being in the length ...
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CAN Extended Frame Figure 19-2. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier SRR IDE SOF SOF IDT28..18 Interframe Arbitration Space Field Remote Frame Bus Idle 11-bit base identifier SRR IDE SOF SOF IDT28..18 Interframe Arbitration Space ...
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Figure 19-3. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Time Quantum (producer) Segments SYNC_SEG (producer) propagation delay Segments (consumer) 19.3.3.2 Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start ...
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Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened to compensate for oscillator tolerances. If, for example, the transmitter oscilla- tor is slower than the receiver oscillator, the ...
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Figure 19-4. Bus Arbitration 19.3.5 Errors The CAN protocol signals any errors immediately as they occur. Three error detection mecha- nisms are implemented at the message level and two at the bit level: 19.3.5.1 Error at Message Level • Cyclic ...
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CAN Controller The CAN controller implemented into ATmega16M1/32M1/64M1 offers V2.0B Active. This full-CAN controller provides the whole hardware for convenient acceptance filtering and message management. For each message to be transmitted or received this module contains one so called ...
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CAN Channel 19.5.1 Configuration The CAN channel can be in: • Enabled mode In this mode: – the CAN channel (internal TxCAN & RxCAN) is enabled – the input clock is enabled • Standby mode In standby mode: – ...
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The total number bit time has to be programmed at least from 8 to 25. Figure 19-7. Sample and Transmission Point CLK Prescaler BRP IO Figure 19-8. General Structure of a Bit Period CLK IO F ...
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Baud Rate With no baud rate prescaler (BRP[5..0]=0) the sampling point comes one time quantum too early. This leads to a fail according the ISO16845 Test plan necessary to lengthen the Phase Segment 1 by one time ...
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Number of MObs This device has 6 MObs, they are numbered from 5). 19.6.2 Operating Modes There is no default mode after RESET. Every MOb has its own fields to control the operating ...
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The MOb is ready to receive a data or a remote frame when the MOb configuration is set (CONMOB) 3. When a frame identifier is received on CAN network, the CAN channel scans all the MObs in receive mode, ...
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Acceptance Filter Upon a reception hit (that is, a good comparison between the ID + RTR + RBn + IDE received and an IDT+ RTRTAG + RBnTAG + IDE specified while taking the comparison mask into account) the IDT ...
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The data index (INDX) is the address pointer to the required data byte. The data byte can be read or write. The data index is automatically incremented after every access if the AINC* bit is reset. A roll-over is implemented, ...
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Error Management 19.8.1 Fault Confinement The CAN channel may be in one of the three following states: • Error active (default): The CAN channel takes part in bus communication and can send an active error frame when the CAN ...
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AERR: Acknowledgment error (Tx only). No detection of the dominant bit in the acknowledge slot Figure 19-13. Error Detection Procedures in a Data Frame Bit error Stuff error Form error Tx ...
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Figure 19-14. CAN Controller Interrupt Structure CANGIE.4 ENTX TXOK[i] CANSTMOB.6 RXOK[i] CANSTMOB.5 BERR[i] CANSTMOB.4 SERR[i] CANSTMOB.3 CERR[i] CANSTMOB.2 FERR[i] CANSTMOB.1 AERR[i] CANSTMOB.0 BXOK CANGIT.4 SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 AERG CANGIT.0 BOFFI CANGIT.6 OVRTIM CANGIT.5 19.9.2 Interrupt Behavior When ...
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Register Description Figure 19-15. Registers Organization AVR Registers General Control General Status General Interrupt Bit Timing 1 Bit Timing 2 Bit Timing 3 Enable MOb 2 Enable MOb 1 Enable Interrupt Enable Interrupt MOb 2 Enable Interrupt MOb 1 ...
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CANGCON – CAN General Control Register Bit Read/Write Initial Value • Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. – request – abort request: a reset of CANEN1 and ...
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The on-going transmission (if exists) is normally terminated and the – enable mode: The CAN channel enters in enable mode once 11 recessive bits • Bit 0 – SWRES: Software Reset Request This ...
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Bit 2 – ENFG: Enable Flag This flag does not generate an interrupt. – CAN controller disable: because an enable/standby command is not immediately – CAN controller enable • Bit 1 – BOFF: Bus Off ...
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Bit 3 – SERG: Stuff Error General Writing a logical one resets this interrupt flag. – interrupt ...
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Bit 4 – ENTX: Enable Transmit Interrupt – interrupt disabled – 1- transmit interrupt enabled • Bit 3 – ENERR: Enable MOb Errors Interrupt – interrupt disabled – 1- MOb errors interrupt enabled • Bit ...
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CANIE2 and CANIE1 – CAN Enable Interrupt MOb Registers Bit Bit Read/Write Initial Value Read/Write Initial Value • Bits 5:0 - IEMOB[5:0]: Interrupt Enable by MOb – interrupt disabled – MOb interrupt enabled Note: • ...
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Bit 6:1 – BRP[5:0]: Baud Rate Prescaler The period of the CAN controller system clock Tscl is programmable and determines the individ- ual bit timing. If ‘BRP[5..0]=0’, see ple Point(s)” on page • Bit 0 – Res: Reserved This ...
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CANBT3 – CAN Bit Timing Register 3 Bit Read/Write Initial Value • Bit 7– Res: Reserved This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT3 is written. • ...
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CANTIML and CANTIMH – CAN Timer Registers Bit Bit Read/Write Initial Value • Bits 15:0 - CANTIM[15:0]: CAN Timer Count CAN timer counter range 0 to 65,535. 19.10.13 CANTTCL and CANTTCH – CAN TTC Timer Registers Bit Bit Read/Write ...
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Bit 3:0 – CGP[3:0]: CAN General Purpose Bits These bits can be pre-programmed to match with the wanted configuration of the CANPAGE register (that is, AINC and INDX2:0 setting). 19.10.17 CANPAGE – CAN Page MOb Register Bit Read/Write Initial ...
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Bit 4 – BERR: Bit Error (Only in Transmission) This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The bit value monitored is different from the bit value ...
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These bits are not cleared once the communication is performed. The user must re-write the configuration to enable a new communication. • This operation is necessary to be able to reset the BXOK flag • This operation also set the ...
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V2.0 part A • Bit 31:21 – IDT[10:0]: Identifier Tag Identifier field of the remote or data frame to send. This field is updated with the corresponding value of the remote or data frame received. • Bit 20:3 – Reserved ...
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CANIDM1, CANIDM2, CANIDM3, and CANIDM4 – CAN Identifier Mask Registers V2.0 part A Bit Bit Read/Write Initial Value V2.0 part B Bit Bit Read/Write Initial Value V2.0 part A • Bit 31:21 – IDMSK[10:0]: Identifier Mask – ...
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Bit 2 – RTRMSK: Remote Transmission Request Mask – comparison true forced – bit comparison enabled • Bit 1 – Reserved Bit Writing zero in this bit is recommended. • Bit 0 – IDEMSK: Identifier ...
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Table 19-2. Examples of CAN Baud Rate Settings for Commonly Frequencies Description CAN f Rate Sampling CLK IO (MHz) (Kbps) Point ( 1000 75 % 500 75 % 250 75 % 16.000 200 75 % 125 75 % ...
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Table 19-2. Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued) Description CAN f Rate Sampling CLK IO (MHz) (Kbps) Point (1) 1000 500 75 % 250 75 % 8.000 200 75 % 125 ...
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LIN / UART - Local Interconnect Network Controller or UART 20.1 Features 20.1.1 LIN • Hardware Implementation of LIN 2.1 (LIN 1.3 Compatibility) • Small, CPU Efficient and Independent Master/Slave Routines Based on “LIN Work Flow Concept” of LIN ...
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LIN Protocol 20.3.1 Master and Slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only. ...
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Data Transport Two types of data may be transported in a frame; signals or diagnostic messages. • Signals Signals are scalar values or byte arrays that are packed into the data field of a frame. A signal is always ...