ATmega8515 Atmel Corporation, ATmega8515 Datasheet - Page 173

• Manufacturer Part Number: ATmega8515
• Manufacturer: Atmel Corporation

Specifications of ATmega8515

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Performing Page Erase by
SPM
Filling the Temporary Buffer
(page loading)
Performing a Page Write
Using the SPM Interrupt
Consideration While Updating
BLS
Prevent Reading the RWW
Section During Self-
Programming
2512K–AVR–01/10
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to
SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1
and R0 is ignored. The page address must be written to PCPAGE in the Z-register.
Other bits in the Z-pointer must be written zero during this operation.
•
•
To write an instruction word, set up the address in the Z pointer and data in R1:R0, write
“00000001” to SPMCR and execute SPM within four clock cycles after writing SPMCR.
The content of PCWORD in the Z-register is used to address the data in the temporary
buffer. The temporary buffer will auto-erase after a Page Write operation or by writing
the RWWSRE bit in SPMCR. It is also erased after a System Reset. Note that it is not
possible to write more than one time to each address without erasing the temporary
buffer.
Note:
To execute Page Write, set up the address in the Z-pointer, write “X0000101” to
SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1
and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-
pointer must be written zero during this operation.
•
•
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt
when the SPMEN bit in SPMCR is cleared. This means that the interrupt can be used
instead of polling the SPMCR Register in software. When using the SPM interrupt, the
Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is
accessing the RWW section when it is blocked for reading. How to move the interrupts
is described in “Interrupts” on page 54.
Special care must be taken if the user allows the Boot Loader section to be updated by
leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can
corrupt the entire Boot Loader, and further software updates might be impossible. If it is
not necessary to change the Boot Loader software itself, it is recommended to program
the Boot Lock bit11 to protect the Boot Loader software from any internal software
changes.
During Self-Programming (either Page Erase or Page Write), the RWW section is
always blocked for reading. The user software itself must prevent that this section is
addressed during the Self-Programming operation. The RWWSB in the SPMCR will be
set as long as the RWW section is busy. During Self-Programming the Interrupt Vector
table should be moved to the BLS as described in “Interrupts” on page 54, or the inter-
rupts must be disabled. Before addressing the RWW section after the programming is
completed, the user software must clear the RWWSB by writing the RWWSRE. See
“Simple Assembly Code Example for a Boot Loader” on page 175 for an example.
Page Erase to the RWW section: The NRWW section can be read during the Page
Erase.
Page Erase to the NRWW section: The CPU is halted during the operation.
Page Write to the RWW section: The NRWW section can be read during the Page
Write.
Page Write to the NRWW section: The CPU is halted during the operation.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded
will be lost.
ATmega8515(L)
173