ATmega8515 Atmel Corporation, ATmega8515 Datasheet - Page 19

• Manufacturer Part Number: ATmega8515
• Manufacturer: Atmel Corporation

Specifications of ATmega8515

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

EEPROM Data Memory
EEPROM Read/Write Access
The EEPROM Address
Register – EEARH and EEARL
2512K–AVR–01/10
The ATmega8515 contains 512 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has
an endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following, specifying the EEPROM Address Registers,
the EEPROM Data Register, and the EEPROM Control Register.
“Memory Programming” on page 179 contains a detailed description on EEPROM Pro-
gramming in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1. A self-timing function, how-
ever, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In heav-
ily filtered power supplies, V
causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page
24. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
• Bits 15..9 – Res: Reserved Bits
These bits are reserved bits in the ATmega8515 and will always read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM
address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed lin-
early between 0 and 511. The initial value of EEAR is undefined. A proper value must be
written before the EEPROM may be accessed.
Bit
Read/Write
Initial Value
EEAR7
R/W
15
R
X
–
7
0
EEAR6
R/W
14
R
X
–
6
0
CC
EEAR5
R/W
13
R
X
–
5
0
is likely to rise or fall slowly on Power-up/down. This
EEAR4
R/W
12
R
–
4
0
X
EEAR3
R/W
11
–
3
R
0
X
EEAR2
R/W
10
R
X
–
2
0
ATmega8515(L)
EEAR1
R/W
R
X
9
–
1
0
EEAR8
EEAR0
R/W
R/W
X
X
8
0
EEARH
EEARL
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