ATmega8515 Atmel Corporation, ATmega8515 Datasheet - Page 42

• Manufacturer Part Number: ATmega8515
• Manufacturer: Atmel Corporation

Specifications of ATmega8515

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Extended MCU Control
Register – EMCUCR
Idle Mode
Power-down Mode
42
ATmega8515(L)
• Bits 7 – SM0: Sleep Mode Select Bit 0
The Sleep Mode Select bits select between the three available sleep modes as shown
in Table 16.
Table 16. Sleep Mode Select
Note:
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter
Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator,
Timer/Counters, Watchdog, and the Interrupt System to continue operating. This sleep
mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-
tus Register – ACSR. This will reduce power consumption in Idle mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the External
Interrupts and the Watchdog continue operating (if enabled). Only an External Reset, a
Watchdog Reset, a Brown-out Reset, an External level interrupt on INT0 or INT1, or an
External interrupt on INT2 can wake up the MCU. This sleep mode basically halts all
generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Inter-
rupts” on page 77 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out period, as described in “Clock Sources” on page
35.
Bit
Read/Write
Initial Value
SM2
0
0
0
0
1
1
1
1
1. Standby mode is only available with external crystals or resonators.
SM0
R/W
7
0
SM1
0
0
1
1
0
0
1
1
SRL2
R/W
CPU
6
0
and clk
SRL1
R/W
5
0
SM0
FLASH
0
1
0
1
0
1
0
1
SRL0
R/W
, while allowing the other clocks to run.
4
0
Sleep Mode
Idle
Reserved
Power-down
Reserved
Reserved
Reserved
Standby
Reserved
SRW01
R/W
3
0
(1)
SRW00
R/W
2
0
SRW11
R/W
1
0
ISC2
R/W
0
0
2512K–AVR–01/10
EMCUCR