ATmega88 Atmel Corporation, ATmega88 Datasheet
ATmega88
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... Power-down mode: 0.1µA at 1.8V Note: 1. See “Data retention” on page 8 ® ® AVR 8-bit microcontroller () 2 C compatible) for details. 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash ATmega48/V ATmega88/V ATmega168/V Rev. 2545T–AVR–05/11 ...
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Pin configurations Figure 1-1. Pinout Atmel ATmega48/88/168. TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (PCINT6/XTAL1/TOSC1) PB6 7 (PCINT7/XTAL2/TOSC2) PB7 8 28 MLF Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 ...
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Pin descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive ...
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The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in 84. 1.1 the supply ...
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Overview The Atmel ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer ...
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... C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu- lators, and Evaluation kits. 2.2 Comparison between Atmel ATmega48, Atmel ATmega88, and Atmel ATmega168 The ATmega48, ATmega88 and ATmega168 differ only in memory sizes, boot loader support, and interrupt vector sizes. for the three devices. Table 2-1. ...
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... ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. ...
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Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. Data retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 ...
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AVR CPU core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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Status register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 0 – C: Carry flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Description” for detailed information. 7.5 General purpose register file The register file is optimized for the AVR enhanced ...
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The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
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SPH and SPL – Stack pointer high and stack pointer low register Bit 0x3E (0x5E) 0x3D (0x5D) Read/write Initial value 7.7 Instruction execution timing This section describes the general access timing concepts for instruction execution. The AVR CPU is ...
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... The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see ATmega88 and Atmel ATmega168” on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...
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Assembly code example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C code example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); ...
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... Since all AVR instructions are bits wide, the Flash is orga- nized as 2K/4K/8K × 16. For software security, the Flash Program memory space is divided into two sections, Boot Loader Section and Application Program Section in ATmega88 and ATmega168. ATmega48 does not have separate Boot Loader and Application Program sec- tions, and the SPM instruction can be executed from the entire Flash ...
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... Figure 8-1. Figure 8-2. 2545T–AVR–05/11 Program memory map, Atmel ATmega48. Program memory Application flash section Program memory map, Atmel ATmega88 and Atmel ATmega168. Program memory Application flash section Boot flash section ATmega48/88/168 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF 18 ...
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SRAM data memory Figure 8-3 The ATmega48/88/168 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space ...
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Figure 8-4. 8.4 EEPROM data memory The Atmel ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory orga- nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of ...
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An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec- ondly, the CPU itself can execute instructions incorrectly, ...
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Register description 8.6.1 EEARH and EEARL – The EEPROM address register Bit 0x22 (0x42) 0x21 (0x41) Read/write Initial value • Bits 15..9 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read ...
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... Step two is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step two can be omitted. See loader support – Read-while-write self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269 Caution: An interrupt between step five and step six will make the write cycle fail, since the EEPROM Master Write Enable will time-out ...
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When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is ...
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Assembly code example EEPROM_write: C code example void EEPROM_write(unsigned int uiAddress, unsigned char ucData 2545T–AVR–05/11 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly code example EEPROM_read: C code example unsigned ...
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System clock and clock options 9.1 Clock systems and their distribution Figure 9-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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Asynchronous timer clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter ...
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Table 9-2. Typical time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V delay will not monitor the actual voltage ...
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Figure 9-2. The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 9-3. Frequency range Notes: The CKSEL0 Fuse ...
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Table 9-4. Oscillator source/ power conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 9.4 Full swing crystal oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting amplifier which ...
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Figure 9-3. Table 9-6. Oscillator source/ power conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising ...
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Low frequency crystal oscillator The device can utilize a 32.768kHz watch crystal as clock source by a dedicated low frequency crystal oscillator. The crystal should be connected as shown in oscillator is selected, start-up times are determined by the ...
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Table 9-8. Notes: When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-9. Table 9-9. Power conditions BOD enabled Fast rising power Slowly rising power Note: 9.7 128kHz internal oscillator The 128kHz ...
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External clock To drive the device from an external clock source, XTAL1 should be driven as shown in 9-4. To run the device on an external clock, the CKSEL fuses must be programmed to “0000” (see Table Table 9-12. ...
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CLKO. If the System Clock Prescaler is used the divided system clock that is output. 9.10 Timer/counter oscillator The device can operate its Timer/Counter2 from an external 32.768kHz ...
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Register description 9.12.1 OSCCAL – Oscillator calibration register Bit (0x66) Read/write Initial value • Bits 7..0 – CAL7..0: Oscillator calibration value The oscillator calibration register is used to trim the calibrated internal RC oscillator to remove process variations from ...
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The CKDIV8 fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of eight at ...
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Power management and sleep modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow and USART transmit complete interrupts. If wake-up from the ana- log comparator interrupt is not required, the analog comparator ...
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If Timer/Counter2 is not running, power-down mode is recommended instead of power-save mode. The Timer/Counter2 can be clocked both synchronously and asynchronously in power-save mode. If Timer/Counter2 is not using the asynchronous clock, the timer/counter oscillator is stopped during sleep. ...
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Brown-out detector If the brown-out detector is not needed by the application, this module should be turned off. If the brown-out detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always ...
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Register description 10.9.1 SMCR – Sleep mode control register The sleep mode control register contains control bits for power management. Bit 0x33 (0x53) Read/write Initial value • Bits 7..4 Res: Reserved bits These bits are unused bits in the ...
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PRR – Power reduction register Bit (0x64) Read/write Initial value • Bit 7 - PRTWI: Power reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up ...
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... JMP – absolute jump – instruction to the reset handling routine. For the Atmel ATmega48 and Atmel ATmega88, the instruction placed at the reset vector must be an RJMP – relative jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...
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Figure 11-1. Reset logic. BODLEVEL [2..0] RSTDISBL 11.3 Power-on reset A power-on reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used ...
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Figure 11-3. MCU start-up, RESET extended externally. TIME-OUT INTERNAL 11.4 External reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see even if the clock is not ...
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Figure 11-5. Brown-out reset during operation. 11.6 Watchdog system reset When the watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the ...
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Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the analog comparator or ADC is used. To reduce power ...
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The watchdog always on (WDTON) fuse, if programmed, will force the watchdog timer to system reset mode. With the fuse programmed the system reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To ...
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Assembly code example WDT_off: C code example void WDT_off(void Note: Note: If the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. ...
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The following code example shows one assembly and one C function for changing the time-out value of the watchdog timer. Assembly code example WDT_Prescaler_Change: C code example void WDT_Prescaler_Change(void Note: Note: The watchdog timer should be reset before ...
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Register description 11.9.1 MCUSR – MCU status register The MCU status register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) Read/write Initial value • Bit 7..4: Res: Reserved bits These bits are unused bits ...
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If WDE is set, the watchdog timer is in interrupt and system reset mode. The first time-out in the watchdog timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the watchdog goes ...
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Bit 5, 2..0 - WDP3..0: Watchdog timer prescaler and 0 The WDP3..0 bits determine the watchdog timer prescaling when the watchdog timer is running. The different prescaling values and their corresponding time-out periods are shown in ...
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... Each interrupt vector occupies two instruction words in ATmega168, and one instruction word in ATmega48 and ATmega88 • ATmega48 does not have a separate boot loader section. In ATmega88 and ATmega168, the reset vector is affected by the BOOTRST fuse, and the interrupt vector start address is affected by the IVSEL bit in MCUCR 12 ...
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Table 12-1. Reset and interrupt vectors in ATmega48. (Continued) Vector no. Program address 22 0x015 23 0x016 24 0x017 25 0x018 26 0x019 The most typical and general program setup for the reset and interrupt vector addresses in the Atmel ...
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... Store program memory ready 1. When the BOOTRST fuse is programmed, the device will jump to the boot loader address at reset, see “Boot loader support – Read-while-write self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269. 2. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot flash section ...
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... Reset and interrupt vectors placement in Atmel ATmega88 IVSEL Reset address 1 0 0x000 1 1 0x000 0 0 Boot reset address 0 1 Boot reset address 1. The boot reset address is shown in means unprogrammed while “ ...
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... When the BOOTRST fuse is programmed and the boot section size set to 2Kbytes, the most typical and general program setup for the reset and interrupt vector addresses in ATmega88 is: Address Labels Code .org 0x001 0x001 0x002 ... 0x019 ; ...
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... Store program memory ready 1. When the BOOTRST fuse is programmed, the device will jump to the boot loader address at reset, see “Boot loader support – Read-while-write self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269. 2. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot flash section ...
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Table 12-5 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is ...
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When the BOOTRST fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program ...
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... Moving interrupts between application and boot space, Atmel ATmega88 and Atmel ATmega168 The MCU control register controls the placement of the interrupt vector table. 12.5 Register description 12.5.1 MCUCR – MCU control register Bit 0x35 (0x55) Read/write Initial value • ...
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Bit 0 – IVCE: Interrupt vector change enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
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External interrupts The external interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins are configured as ...
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Register description 13.2.1 EICRA – External interrupt control register A The external interrupt control register A contains control bits for interrupt sense control. Bit (0x69) Read/write Initial value • Bit 7..4 – Res: Reserved bits These bits are unused ...
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EIMSK – External interrupt mask register Bit 0x1D (0x3D) Read/write Initial value • Bit 7..2 – Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 1 – INT1: ...
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PCICR – Pin change interrupt control register Bit (0x68) Read/write Initial value • Bit 7..3 - Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 2 - PCIE2: ...
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Bit 0 - PCIF0: Pin change interrupt flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), ...
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I/O-ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 14.2 Ports as general digital I/O The ports are bi-directional I/O ports ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 14-3. Synchronization when reading an externally applied pin value. INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
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Assembly code example C code example unsigned char i; Note: 14.2.5 Digital input enable and sleep modes As shown in input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in ...
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Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable ...
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Table 14-2 ure 14-5 on page 76 generated internally in the modules having the alternate function. Table 14-2. Signal name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for ...
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Alternate functions of port B The port B pins with alternate functions are shown in Table 14-3. Port pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • XTAL2/TOSC2/PCINT7 – Port B, ...
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TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the AS2 bit in ASSR is set (one) to ...
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OC1A/PCINT1 – Port B, bit 1 OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set (one)) ...
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Notes: Table 14-5. Signal name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 14.3.2 Alternate functions of port C The port C pins with alternate functions are shown in Table 14-6. Port pin The alternate pin configuration is ...
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RESET/PCINT14 – Port C, bit 6 RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset ...
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PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. • ADC0/PCINT8 – Port C, bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses ...
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Alternate functions of port D The port D pins with alternate functions are shown in Table 14-9. Port pin The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, bit 7 AIN1, Analog Comparator Negative Input. Configure ...
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T1/OC0B/PCINT21 – Port D, bit 5 T1, Timer/Counter1 counter source. OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PD5 pin has to be configured as an ...
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Table 14-10. Overriding signals for alternate functions PD7..PD4. Signal name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 14-11. Overriding signals for alternate functions in PD3..PD0. Signal name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...
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Register description 14.4.1 MCUCR – MCU control register Bit 0x35 (0x55) Read/write Initial value • Bit 4 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the ...
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PORTD – The port D data register Bit 0x0B (0x2B) Read/write Initial value 14.4.9 DDRD – The port D data direction register Bit 0x0A (0x2A) Read/write Initial value 14.4.10 PIND – The port D input pins address Bit 0x09 ...
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Timer/Counter0 with PWM 15.1 Features • Two independent output compare units • Double buffered output compare registers • Clear timer on compare match (auto reload) • Glitch free, phase correct pulse width modulator (PWM) • Variable PWM period ...
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Figure 15-1. 8-bit timer/counter block diagram. 15.2.1 Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output ...
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The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The ...
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The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the ...
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The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis- abled the CPU will access the OCR0x ...
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Figure 15-4. Compare match output unit, schematic. The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out- put) ...
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Normal mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum ...
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The waveform generated will have a maximum frequency when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: The N variable represents the ...
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In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to ...
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Figure 15-7. Phase correct PWM mode, timing diagram. TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches ...
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BOTTOM the OCnx value at MAX must correspond to the result of an up- counting Compare Match • The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the Compare ...
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Figure 15-10. Timer/counter timing diagram, setting of OCF0x, with prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 15-11 PWM mode where OCR0A is TOP. Figure 15-11. Timer/counter timing diagram, clear timer on compare match mode, with pres- clk clk ...
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Register description 15.9.1 TCCR0A – Timer/counter control register A Bit 0x24 (0x44) Read/write Initial value • Bits 7:6 – COM0A1:0: Compare match output A mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
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Table 15-4 rect PWM mode. Table 15-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare match output B mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...
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Note: Table 15-7 rect PWM mode. Table 15-7. COM0B1 Note: • Bits 3, 2 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bits 1:0 ...
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TCCR0B – Timer/counter control register B Bit 0x25 (0x45) Read/write Initial value • Bit 7 – FOC0A: Force output compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...
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Table 15-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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TIMSK0 – Timer/counter interrupt mask register Bit (0x6E) Read/write Initial value • Bits 7..3 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bit 2 – OCIE0B: Timer/counter ...
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Bit 0 – TOV0: Timer/Counter0 overflow flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one ...
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Timer/Counter1 with PWM 16.1 Features • True 16-bit design (that is, allows 16-bit PWM) • Two independent output compare units • Double buffered output compare registers • One input capture unit • Input capture noise canceler • Clear ...
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Figure 16-1. 16-bit timer/counter block diagram Note: 16.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
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Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture ...
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Assembly code examples C code examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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Assembly code example TIM16_ReadTCNT1: C code example unsigned int TIM16_ReadTCNT1( void ) { } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. The following code examples show how atomic write of ...
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Assembly code example TIM16_WriteTCNT1: C code example void TIM16_WriteTCNT1( unsigned int Note: The assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to TCNT1. 16.3.1 Reusing the temporary high ...
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Counter unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 Figure 16-2. Counter unit block diagram. Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
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Input capture unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ...
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Input capture trigger source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is ...
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Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ- ing a logical one to its I/O bit location. The Waveform ...
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However good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Reg- ister since the compare of all 16 bits ...
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Figure 16-5. Compare match output unit, schematic. COMnx1 COMnx0 FOCnx clk The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction ...
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The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM out- put generated should be inverted or not (inverted or non-inverted ...
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Figure 16-6. CTC mode, timing diagram. TCNTn OCnA (toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define ...
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The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 ...
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When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next ...
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OCR1A set to MAX). The PWM reso- lution in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter ...
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TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period ...
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OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively ...
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Figure 16-11. Timer/counter timing diagram, setting of OCF1x, with prescaler (f Figure 16-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...
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Figure 16-13 Figure 16-13. Timer/counter timing diagram, with prescaler (f and ICF n 2545T–AVR–05/11 shows the same timing data, but with the prescaler enabled. clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP ...
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Register description 16.11.1 TCCR1A – Timer/Counter1 control register A Bit (0x80) Read/write Initial value • Bit 7:6 – COM1A1:0: Compare output mode for channel A • Bit 5:4 – COM1B1:0: Compare output mode for channel B The COM1A1:0 and ...
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Note: Table 16-3 correct or the phase and frequency correct, PWM mode. Table 16-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform generation mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence ...
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Table 16-4. Waveform generation mode bit description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
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The FOC1A/FOC1B bits are always read as zero. 16.11.4 TCNT1H and TCNT1L – Timer/Counter1 Bit (0x85) (0x84) Read/write Initial value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, ...
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ICR1H and ICR1L – Input capture register 1 Bit (0x87) (0x86) Read/write Initial value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator ...
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TIFR1 – Timer/Counter1 interrupt flag register Bit 0x16 (0x36) Read/write Initial value • Bit 7, 6 – Res: Reserved bits These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero. • Bit 5 – ...
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Timer/Counter0 and Timer/Counter1 prescalers “8-bit Timer/Counter0 with PWM” on page 89 108 share the same prescaler module, but the Timer/Counters can have different prescaler set- tings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.0.1 Internal clock source ...
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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...
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Register description 17.1.1 GTCCR – General timer/counter control register Bit 0x23 (0x43) Read/write Initial value • Bit 7 – TSM: Timer/counter synchronization mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value ...
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Timer/Counter2 with PWM and asynchronous operation 18.1 Features • Single channel counter • Clear timer on compare match (auto reload) • Glitch-free, phase correct pulse width modulator (PWM) • Frequency generator • 10-bit clock prescaler • Overflow and ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...
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Figure 18-2. Counter unit block diagram. Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 18-3. Output compare unit, block diagram. The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...
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The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit in ...
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Compare output mode and waveform generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1 tells the Waveform Generator that no action on the OC2x Register ...
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Figure 18-5. CTC mode, timing diagram. TCNTn OCnx (toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for ...
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OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 18.7.4 Phase correct PWM mode ...
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COM2x1:0 to three. TOP is defined as 0xFF when WGM2 and OCR2A when MGM2 (See value will only be visible on the port pin if the data direction for ...
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Figure 18-9. Timer/counter timing diagram, with prescaler (f clk clk (clk TCNTn TOVn Figure 18-10 Figure 18-10. Timer/counter timing diagram, setting of OCF2A, with prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 18-11 Figure 18-11. Timer/counter timing diagram, clear ...
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Asynchronous operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching ...
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Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, ...
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The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port ...
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Table 18-3. COM2A1 Note: Table 18-4 rect PWM mode. Table 18-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare match output B mode These bits control the Output Compare pin (OC2B) behavior. ...
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Table 18-6 mode. Table 18-6. COM2B1 Note: Table 18-7 rect PWM mode. Table 18-7. COM2B1 Note: • Bits 3, 2 – Res: Reserved bits These bits are reserved bits in the Atmel ...
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Table 18-8. Mode Notes: 18.11.2 TCCR2B – Timer/counter control register B Bit (0xB1) Read/write Initial value • Bit 7 – FOC2A: Force output compare A The FOC2A bit is only active when ...
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A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved bits These bits are reserved ...
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The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2A pin. 18.11.5 ...
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Bit 1 – OCF2A: Output compare flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing ...
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Bit 1 – TCR2AUB: Timer/counter control Register2 update busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical ...
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SPI – Serial peripheral interface 19.1 Features • Full-duplex, three-wire synchronous data transfer • Master or slave operation • LSB first or MSB first data transfer • Seven programmable bit rates • End of transmission interrupt flag • Write ...
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Figure 19-1. SPI block diagram Note: The interconnection between Master and Slave CPUs with SPI is shown in 163. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling ...
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Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The ...
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Assembly code example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C code example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 2545T–AVR–05/11 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly code example SPI_SlaveInit: SPI_SlaveReceive: C code example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 2545T–AVR–05/11 (1) ; ...
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SS pin functionality 19.3.1 Slave mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Table 19-2. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 19-3. SPI transfer format with CPHA = 0. Figure 19-4. SPI transfer format with CPHA = 1. 2545T–AVR–05/11 CPOL functionality. Leading edge Sample (rising) Setup (rising) Sample (falling) Setup ...
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Register description 19.5.1 SPCR – SPI control register Bit 0x2C (0x4C) Read/write Initial value • Bit 7 – SPIE: SPI interrupt enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...
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Bits 1, 0 – SPR1, SPR0: SPI clock rate select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...
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SPDR – SPI data register Bit 0x2E (0x4E) Read/write Initial value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...
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USART0 20.1 Features • Full duplex operation (independent serial receive and transmit registers) • Asynchronous or synchronous operation • Master or slave clocked synchronous operation • High resolution baud rate generator • Supports serial frames with ...
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Figure 20-1. USART block diagram Note: 20.3 Clock generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave ...
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Figure 20-2. Clock generation logic, block diagram. Signal description osc 20.3.1 Internal clock generation – The baud rate generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The ...
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Table 20-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 20-1. Operating mode Asynchronous normal mode (U2Xn = 0) Asynchronous double speed mode (U2Xn = 1) Synchronous master mode Note: BAUD f ...
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External clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. ...
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A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted ...
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Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be ...
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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly code example USART_Init: C code example #define FOSC 1843200 // Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) ...
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Data transmission – The USART transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by ...
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The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into ...
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Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) ...
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The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be ...
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Assembly code example USART_Receive: USART_ReceiveNoError: C code example unsigned int USART_Receive( void ) { } Note: 2545T–AVR–05/11 (1) ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer ...
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Receive complete flag and interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...
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Figure 20-5. Start bit sampling. When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the ...
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Figure 20-7. Stop bit sampling and next start bit sampling. The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...
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Table 20-2. # (Data+parity bit) Table 20-3. # (Data+parity bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...
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When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit ...
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Register description 20.10.1 UDRn – USART I/O data register n Bit Read/write Initial value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...
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UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame error This bit is set if the next character in the receive buffer had a Frame Error when received, that is, ...
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Bit 5 – UDRIEn: USART data register empty interrupt enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, ...
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Bits 5:4 – UPMn1:0: Parity mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
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Table 20-8. UCPOLn 0 1 20.10.5 UBRRnL and UBRRnH – USART baud rate registers Bit Read/write Initial value • Bit 15:12 – Reserved bits These bits are reserved for future use. For compatibility with future devices, these bit must be ...
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Table 20-9. Examples of UBRRn settings for commonly used oscillator frequencies 1.0000MHz osc Baud U2Xn = 0 rate (bps) UBRRn Error UBRRn 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 -7.0% 12 14.4k 3 8.5% 8 ...
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Table 20-10. Examples of UBRRn settings for commonly used oscillator frequencies 3.6864MHz osc Baud U2Xn = 0 U2Xn = 1 rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% 47 14.4k ...
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Table 20-11. Examples of UBRRn settings for commonly used oscillator frequencies 8.0000MHz osc Baud U2Xn = 0 U2Xn = 1 rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k ...
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Table 20-12. Examples of UBRRn settings for commonly used oscillator frequencies 16.0000MHz osc Baud U2Xn = 0 U2Xn = 1 rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% 207 14.4k ...
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USART in SPI mode 21.1 Features • Full duplex, three-wire synchronous data transfer • Master operation • Supports all four SPI modes of operation (mode and 3) • LSB first or MSB first data transfer (configurable ...
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Table 21-1. Operating mode Synchronous Master mode Note: BAUD f OSC UBRRn 21.4 SPI data modes and timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn ...