ATtiny13

Manufacturer Part NumberATtiny13
ManufacturerAtmel Corporation
ATtiny13 datasheets
 

Specifications of ATtiny13

Flash (kbytes)1 KbytesPin Count8
Max. Operating Frequency20 MHzCpu8-bit AVR
Hardware Qtouch AcquisitionNoMax I/o Pins6
Ext Interrupts6Usb SpeedNo
Usb InterfaceNoGraphic LcdNo
Video DecoderNoCamera InterfaceNo
Adc Channels4Adc Resolution (bits)10
Adc Speed (ksps)15Analog Comparators1
Resistive Touch ScreenNoTemp. SensorNo
Crypto EngineNoSram (kbytes)0.06
Eeprom (bytes)64Self Program MemoryYES
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers1Output Compare Channels2
Pwm Channels232khz RtcNo
Calibrated Rc OscillatorYes  
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Features
High Performance, Low Power AVR
Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Througput at 20 MHz
High Endurance Non-volatile Memory segments
– 1K Bytes of In-System Self-programmable Flash program memory
– 64 Bytes EEPROM
– 64 Bytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C (see
– Programming Lock for Self-Programming Flash & EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
– 20-pad MLF: Six Programmable I/O Lines
Operating Voltage:
– 1.8 - 5.5V for ATtiny13V
– 2.7 - 5.5V for ATtiny13
Speed Grade
– ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 240 µA
– Power-down Mode:
• < 0.1 µA at 1.8V
®
8-Bit Microcontroller
page
6)
8-bit
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
ATtiny13
ATtiny13V
Rev. 2535J–AVR–08/10

ATtiny13 Summary of contents

  • Page 1

    ... Operating Voltage: – 1.8 - 5.5V for ATtiny13V – 2.7 - 5.5V for ATtiny13 • Speed Grade – ATtiny13V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATtiny13 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Industrial Temperature Range • Low Power Consumption – Active Mode: • 1 MHz, 1.8V: 240 µA – Power-down Mode: • ...

  • Page 2

    ... Pin Configurations Figure 1-1. Pinout ATtiny13/ATtiny13V (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect ...

  • Page 3

    ... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13 as listed on 1.1.4 RESET Reset input ...

  • Page 4

    ... Overview The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

  • Page 5

    ... On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface conventional non-volatile memory programmer On-chip boot code running on the AVR core. The ATtiny13 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits. 2535J–AVR–08/10 ...

  • Page 6

    ... C is compiler dependent. Please confirm with the C compiler documen- tation for more details. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATtiny13 6 2535J–AVR–08/10 ...

  • Page 7

    CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...

  • Page 8

    ... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny13 8 2535J–AVR–08/10 ...

  • Page 9

    SREG – Status Register Bit Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed ...

  • Page 10

    ... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in ATtiny13 10 shows the structure of the 32 general purpose working registers in the CPU. ...

  • Page 11

    Figure 4-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing ...

  • Page 12

    ... The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address the higher is the ATtiny13 12 , directly generated from the selected clock source for the ...

  • Page 13

    RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic ...

  • Page 14

    ... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny13 14 ; set Global Interrupt Enable 2535J–AVR–08/10 ...

  • Page 15

    ... The ATtiny13 contains 1K byte On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are bits wide, the Flash is organized as 512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny13 Pro- gram Counter (PC) is nine bits wide, thus addressing the 512 Program memory locations. ...

  • Page 16

    ... EEPROM Data Memory The ATtiny13 contains 64 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

  • Page 17

    The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In ...

  • Page 18

    ... Wait for completion of previous write */ while(EECR & (1<<EEPE)) /* Set Programming mode */ EECR = (0<<EEPM1)|(0>>EEPM0) /* Set up address and data registers */ EEARL = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } ATtiny13 18 r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; 2535J–AVR–08/10 ...

  • Page 19

    The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...

  • Page 20

    ... I/O Memory The I/O space definition of the ATtiny13 is shown in All ATtiny13 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...

  • Page 21

    ... Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read ATtiny13. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny13 and will always read as zero. • ...

  • Page 22

    ... When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read opera- tion write operation is in progress neither possible to read the EEPROM, nor to change the EEARL Register. ATtiny13 22 2535J–AVR–08/10 ...

  • Page 23

    System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

  • Page 24

    ... Table 6-2. 6.2.1 External Clock To drive the device from an external clock source, CLKI should be driven as shown run the device on an external clock, the CKSEL fuses must be programmed to “00”. Figure 6-2. ATtiny13 24 Device Clocking Options Select page 24) page 26) 1. For all fuses “1” means unprogrammed while “0” means programmed. ...

  • Page 25

    When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-3. Table 6-3. SUT1.. When applying an external clock required to avoid sudden changes in the ...

  • Page 26

    ... In-System or High-voltage Programmer. 6.3 System Clock Prescaler The ATtiny13 system clock can be divided by setting the page 28. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...

  • Page 27

    ... Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved bit in ATtiny13 and it will always read zero. • Bits 6:0 – CAL[6:0]: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process vari- ations from the Oscillator frequency. This is done automatically during Chip Reset. When OSCCAL is zero, the lowest available frequency is chosen ...

  • Page 28

    ... CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock ...

  • Page 29

    Table 6-8. CLKPS3 2535J–AVR–08/10 Clock Prescaler Select (Continued) CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 1 Reserved 0 Reserved 1 ...

  • Page 30

    ... Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator ATtiny13 30 presents the different clock systems in the ATtiny13, and their distribu- Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domains X ...

  • Page 31

    Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When the SM[1:0] bits are written to ...

  • Page 32

    ... To avoid the MCU entering the sleep mode unless it is the programmer’s purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. ATtiny13 32 for details on the start-up time. ...

  • Page 33

    ... Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1:0 These bits select between the three available sleep modes as shown in Table 7-2. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny13 and will always read as zero. 2535J–AVR–08/10 Sleep Mode Select SM1 ...

  • Page 34

    ... This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL fuses. The differ- ent selections for the delay period are presented in ATtiny13 34 Figure 8-1 on page 34 defines the electrical parameters of the reset circuitry. ...

  • Page 35

    ... Reset Sources The ATtiny13 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. ...

  • Page 36

    ... Figure 8-4. 8.1.3 Brown-out Detection ATtiny13 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...

  • Page 37

    ... Watchdog Timer ATtiny13 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out 2535J– ...

  • Page 38

    ... WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. ATtiny13 38 Watchdog Timer 128kHz ...

  • Page 39

    The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of ...

  • Page 40

    ... WDTCR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); } Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. ATtiny13 40 (1) r16, WDTCR r16, (1<<WDCE) | (1<<WDE) WDTCR, r16 Got four cycles to set the new values from here - r16, (1< ...

  • Page 41

    ... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...

  • Page 42

    ... The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 8-2 on page Table 8-2. WDP3 ATtiny13 42 Watchdog Timer Configuration (1) WDE WDTIE Mode 0 0 Stopped 0 1 Interrupt Mode 1 0 ...

  • Page 43

    Table 8-2. WDP3 2535J–AVR–08/10 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 Typical ...

  • Page 44

    ... Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny13. For a general explanation of the AVR interrupt handling, refer to page 12. 9.1 Interrupt Vectors The interrupt vectors of ATtiny13 are described in Table 9-1. Vector No. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...

  • Page 45

    External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as out- puts. This feature ...

  • Page 46

    ... Initial Value • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...

  • Page 47

    ... Initial Value • Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 5:0 – PCINT5:0: Pin Change Enable Mask 5:0 Each PCINT5:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. ...

  • Page 48

    ... Using the I/O port as General Digital I/O is described in 49. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Functions” on page nate functions. ATtiny13 48 and Ground as indicated in CC for a complete list of parameters. ...

  • Page 49

    Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...

  • Page 50

    ... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. page 51 value. The maximum and minimum propagation delays are denoted t respectively. ATtiny13 50 summarizes the control signals for the pin value. Port Pin Configurations PUD ...

  • Page 51

    Figure 10-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS SYNC LATCH Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and ...

  • Page 52

    ... If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the ATtiny13 52 (1) r16,(1< ...

  • Page 53

    Sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.2.6 Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of ...

  • Page 54

    ... Refer to the alternate function description for further details. 10.3.1 Alternate Functions of Port B The Port B pins with alternate function are shown in ATtiny13 54 summarizes the function of the overriding signals. The pin and port Figure 10-5 on page 53 are not shown in the succeeding tables. The overriding ...

  • Page 55

    Table 10-3. Table 10-4 shown in Table 10-4. Signal PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 2535J–AVR–08/10 Port B Pins Alternate Functions Port Pin Alternate Function RESET: Reset Pin dW: debugWIRE I/O PB5 ADC0: ADC ...

  • Page 56

    ... Initial Value • Bits 7, 2– Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See figuring the Pin” ...

  • Page 57

    PINB – Port B Input Pins Address Bit Read/Write Initial Value 2535J–AVR–08/ – – PINB5 PINB4 R R R/W R N/A N PINB3 PINB2 PINB1 PINB0 R/W R/W R/W ...

  • Page 58

    ... I/O pins, refer to ble I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 11-1. 8-bit Timer/Counter Block Diagram ATtiny13 58 “Pinout ATtiny13/ATtiny13V” on page “Register Description” on page Count Clear Control Logic Direction ...

  • Page 59

    Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with ...

  • Page 60

    ... The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 11-3 on page 61 ATtiny13 60 DATA BUS count clear ...

  • Page 61

    Figure 11-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...

  • Page 62

    ... Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi- ble on the pin. The port override function is independent of the Waveform Generation mode. ATtiny13 62 Waveform ...

  • Page 63

    The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. 11.6.1 Compare Output Mode and Waveform Generation ...

  • Page 64

    ... Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited ATtiny13 64 Figure 11-5 on page ...

  • Page 65

    DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The ...

  • Page 66

    ... The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 11-7. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period ATtiny13 OC0 clk_I/O 66. The TCNT0 value is in the timing diagram shown as a histogram for when OCR0A is set to zero ...

  • Page 67

    The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows ...

  • Page 68

    ... I/O TCNTn OCRnx OCFnx Figure 11-11 on page 69 and fast PWM mode where OCR0A is TOP. ATtiny13 68 MAX - 1 MAX shows the same timing data, but with the prescaler enabled. MAX - 1 MAX shows the setting of OCF0B in all modes and OCF0A in all modes except CTC OCRnx - 1 ...

  • Page 69

    Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk I/O clk Tn (clk /8) I/O TCNTn (CTC) OCRnx OCFnx 11.9 Register Description 11.9.1 TCCR0A – Timer/Counter Control Register A Bit Read/Write Initial Value • Bits ...

  • Page 70

    ... However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to enable the output driver. When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the WGM02:0 bit setting. Table 11-5 on page 71 a normal or CTC mode (non-PWM). ATtiny13 70 Compare Output Mode, Fast PWM Mode COM00 Description 0 Normal port operation, OC0A disconnected ...

  • Page 71

    ... Table 11-7. COM0A1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. 2535J–AVR–08/10 Compare Output Mode, non-PWM Mode COM00 Description 0 Normal port operation, OC0B disconnected. 1 Toggle OC0B on Compare Match ...

  • Page 72

    ... Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. ATtiny13 72 Table 11-8 on page Waveform Generation Mode Bit Description Timer/Counter ...

  • Page 73

    ... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...

  • Page 74

    ... Initial Value • Bits 7:4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...

  • Page 75

    ... Initial Value • Bits 7:4, 0 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...

  • Page 76

    ... Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f ATtiny13 76 ). Alternatively, one of four taps from the prescaler can be used as a ...

  • Page 77

    However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) ...

  • Page 78

    ... Analog Comparator, as shown in 13-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. Table 13-1. ACME ATtiny13 78 78. ACBG (1) 2, Table 10-5 on page 56, and Analog Comparator Multiplexed Input ADEN MUX1..0 ...

  • Page 79

    ... When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com- parator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny13 and will always read as zero. 2535J–AVR–08/10 7 ...

  • Page 80

    ... PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. ATtiny13 80 Table 13-2 on page ...

  • Page 81

    ... ADC Start Conversion by Auto Triggering on Interrupt Sources • Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler 14.2 Overview The ATtiny13 features a 10-bit successive approximation ADC. A block diagram of the ADC is shown in Figure 14-1. Analog to Digital Converter Block Schematic V CC ADC3 ADC2 ADC1 ADC0 2535J– ...

  • Page 82

    ... Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. ATtiny13 82 CC 2535J–AVR–08/10 ...

  • Page 83

    Figure 14-2. ADC Auto Trigger Logic Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly ...

  • Page 84

    ... ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. Figure 14-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL ATtiny13 84 Figure 14-4 below. First Conversion ...

  • Page 85

    When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 14-6 this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional ...

  • Page 86

    ... Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. ATtiny13 86 Table 14-1 ...

  • Page 87

    ADC Voltage Reference The reference voltage for the ADC (V ended channels that exceed V either V voltage source may be inaccurate, and the user is advised to discard this result. 14.7 ADC Noise Canceler The ADC features a ...

  • Page 88

    ... ADC Noise Reduction Mode 14.10 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior: ATtiny13 88 and GND pins as possible. CC Section 14.7 on page 87 ...

  • Page 89

    Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 14-9. Offset Error Output Code • Gain Error: After adjusting for offset, the Gain Error is ...

  • Page 90

    ... Figure 14-11. Integral Non-linearity (INL) Output Code • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 14-12. Differential Non-linearity (DNL) ATtiny13 90 Output Code 0x3FF 1 LSB ...

  • Page 91

    ... Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved bit in the ATtiny13 and will always read as zero. • Bit 6 – REFS0: Reference Selection Bit This bit selects the voltage reference for the ADC, as shown in during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set) ...

  • Page 92

    ... Bits 4:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 1:0 – MUX1:0: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 14-3 on page 92 will not go in effect until this conversion is complete (ADIF in ADCSRA is set) ...

  • Page 93

    Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter- rupt is activated. • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These ...

  • Page 94

    ... Initial Value • Bits 7, 5:3 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and will always read as zero. • Bits 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion ...

  • Page 95

    On-chip Debug System 15.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...

  • Page 96

    ... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATtiny13 96 will not work. CC ® will insert a BREAK instruction in the Program memory. The instruc- ...

  • Page 97

    Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...

  • Page 98

    ... This is shown in addressed independently. Therefore major importance that the software addresses the same page in both the Page Erase and Page Write operation. Figure 16-1. Addressing the Flash During SPM Z - REGISTER Note: ATtiny13 98 The CPU is halted during the Page Write operation ...

  • Page 99

    The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. 16.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation ...

  • Page 100

    ... Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. typical programming time for Flash accesses from the CPU. Table 16-1. Flash write (Page Erase, Page Write, and write lock bits by SPM) Note: ATtiny13 100 FHB7 FHB6 FHB5 “ ...

  • Page 101

    ... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny13 and always read as zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. • ...

  • Page 102

    ... This section describes how ATtiny13 memories can be programmed. 17.1 Program And Data Memory Lock Bits ATtiny13 provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in erased to “1” with the Chip Erase command, only. ...

  • Page 103

    ... Fuse Bytes The ATtiny13 has two fuse bytes. briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 17-3. Fuse Bit – – ...

  • Page 104

    ... Calibration Bytes The signature area of the ATtiny13 contains two bytes of calibration data for the internal oscilla- tor. The calibration data in the high byte of address 0x00 is for use with the oscillator set to 9.6 MHz operation. During reset, this byte is automatically written into the OSCCAL register to ensure correct frequency of the oscillator ...

  • Page 105

    Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). See Figure 17-1. ...

  • Page 106

    ... Serial Programming Algorithm When writing serial data to the ATtiny13, data is clocked on the rising edge of SCK. When reading data from the ATtiny13, data is clocked on the falling edge of SCK. See 18-5 on page 121 To program and verify the ATtiny13 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in 1 ...

  • Page 107

    Table 17-8. Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE 17.6.2 Serial Programming Instruction set The instruction set is described in Table 17-9. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 ...

  • Page 108

    ... Low byte High Byte data out data in don’t care 17.7 High-Voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data mem- ory, lock bits and fuse bits in the ATtiny13. Figure 17-2. High-voltage Serial Programming ATtiny13 108 ...

  • Page 109

    ... SII SDO 17.7.1 High-Voltage Serial Programming Algorithm To program and verify the ATtiny13 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed in 2. Apply 4.5 - 5.5V between VCC and GND. Ensure that Vcc reaches at least 1.8V within the next 20µ ...

  • Page 110

    ... Exit Programming mode by power the device down or by bringing RESET pin to 0V. Table 17-12. High-voltage Reset Characteristics Supply Voltage V CC 4.5V 5.5V 17.7.2 High-Voltage Serial Programming Instruction set The instruction set is described in Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13 Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx ...

  • Page 111

    ... Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13 (Continued) Instruction Instr.1/5 SDI 0_00bb_bbbb_00 Load EEPROM SII 0_0000_1100_00 Page Buffer SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Program SII 0_0110_0100_00 EEPROM Page SDO x_xxxx_xxxx_xx SDI 0_00bb_bbbb_00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Write EEPROM Byte SDI 0_0000_0000_00 ...

  • Page 112

    ... Table 17-13. High-Voltage Serial Programming Instruction Set for ATtiny13 (Continued) Instruction Instr.1/5 SDI 0_0000_1000_00 Read Signature SII 0_0100_1100_00 Bytes SDO x_xxxx_xxxx_xx SDI 0_0000_1000_00 Read SII 0_0100_1100_00 Calibration Byte SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Load “No Operation” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx Note address high bits address low bits data in high bits data in low bits data out high bits data out low bits don’ ...

  • Page 113

    ... Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny13, data is clocked on the rising edge of the serial clock, see for details. Figure 17-3. Addressing the Flash which is Organized in Pages PROGRAM MEMORY 2535J– ...

  • Page 114

    ... Read EEPROM Byte. The contents at the selected address are available at serial out- put SDO. 17.8.6 Programming and Reading the Fuse and Lock Bits The algorithms for programming and reading the fuse low/high bits and lock bits are shown in Table 17-13 on page ATtiny13 114 MSB MSB MSB 0 ...

  • Page 115

    Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in page 110. 17.8.8 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V 18. Electrical Characteristics 18.1 ...

  • Page 116

    ... Although each I/O port can under non-transient, steady state conditions source more than the test conditions, the sum of all I (for all ports) should not exceed 60 mA are not guaranteed to source current greater than the listed test condition. ATtiny13 116 = -40°C to +85°C (Continued) A Condition Min ...

  • Page 117

    ... V Figure 18-1. Maximum Frequency vs MHz Figure 18-2. Maximum Frequency vs. V 2535J–AVR–08/10 18-2, the maximum frequency vs. V < 4.5V MHz 1.8V 20 MHz 10 MHz 2.7V As shown in CC. relationship is linear between 1.8V < for ATtiny13V CC Safe Operating Area 2.7V for ATtiny13 CC Safe Operating Area 4.5V 5.5V Figure 18-1 and < 2.7V CC 5.5V 117 ...

  • Page 118

    ... ATtiny13 118 149, Figure 19-53 on page 150 Fixed voltage within: (2) 1.8V – 5.5V (3) 2.7V – 5.5V 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). 2. Voltage range for ATtiny13V. 3. Voltage range for ATtiny13. V IH1 V IL1 V = 1.8 - 5.5V CC Min. 0 250 100 100 Figure 19-50 on page 148, Figure 19-51 on page ...

  • Page 119

    System and Reset Characteristics Table 18-4. Reset, Brown-out and Internal Voltage Reference Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V Power-on Reset Threshold Voltage POT (1) (falling) V RESET Pin Threshold Voltage RST t Minimum pulse width on ...

  • Page 120

    ... Differential Non-linearity (DNL) Gain Error Offset Error Conversion Time Clock Frequency V Input Voltage IN Input Bandwidth V Internal Voltage Reference INT R Analog Input Resistance AIN ATtiny13 120 = -40°C to +85°C A Condition 4V, REF CC ADC clock = 200 kHz REF CC ADC clock = 1 MHz ...

  • Page 121

    ... Otherwise Noted) Parameter Oscillator Frequency (ATtiny13V, V Oscillator Period (ATtiny13V Oscillator Frequency (ATtiny13, V Oscillator Period (ATtiny13 2.7 - 5.5V) CC Oscillator Frequency (ATtiny13, V Oscillator Period (ATtiny13 4.5V - 5.5V) CC SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High for f < ...

  • Page 122

    ... SDI (PB0), SII (PB1) Table 18-9. Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB ATtiny13 122 t IVSH SCI (PB3) SDO (PB2) High-voltage Serial Programming Characteristics T = 25° 5.0V ± 10% (Unless otherwise noted Parameter SCI (PB3) Pulse Width High SCI (PB3) Pulse Width Low ...

  • Page 123

    Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...

  • Page 124

    ... Figure 19-2. Active Supply Current vs. Frequency ( MHz) Figure 19-3. Active Supply Current vs. V ATtiny13 124 ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 Frequency (MHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 9 1 20MH 4 ...

  • Page 125

    Figure 19-4. Active Supply Current vs. V Figure 19-5. Active Supply Current vs. V 0.14 0.12 0.08 0.06 0.04 0.02 2535J–AVR–08/10 ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4.8 MH 4.5 4 3.5 3 2.5 2 1.5 1 0.5 ...

  • Page 126

    ... Figure 19-6. Active Supply Current vs. V 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 19.2 Idle Supply Current Figure 19-7. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ATtiny13 126 CC ACTIVE SUPPLY CURRENT vs kHz EXTERNAL CLOCK 0 1.5 2 2 IDLE SUPPLY CURRENT vs. LOW FREQUENCY (0.1 - 1.0 MHz 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) (32 kHz External Clock ° ...

  • Page 127

    Figure 19-8. Idle Supply Current vs. Frequency ( MHz) Figure 19-9. Idle Supply Current vs. V 2535J–AVR–08/10 IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20MHz 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 1 ...

  • Page 128

    ... Figure 19-10. Idle Supply Current vs. V 1.2 0.8 0.6 0.4 0.2 Figure 19-11. Idle Supply Current vs. V ATtiny13 128 (Internal RC Oscillator, 4.8 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 1.5 2 2 (Internal RC Oscillator, 128 kHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL WD OSCILLATOR, 128 KH 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 1 -40 ° ...

  • Page 129

    Figure 19-12. Idle Supply Current vs. V 19.3 Power-Down Supply Current Figure 19-13. Power-Down Supply Current vs. V 2535J–AVR–08/10 (32 kHz External Clock) CC IDLE SUPPLY CURRENT vs. V 32kHz EXTERNAL CLOCK ...

  • Page 130

    ... Figure 19-14. Power-Down Supply Current vs. V 19.4 Pin Pull-up Figure 19-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 160 140 85 ˚C 120 100 ATtiny13 130 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1.5 2 2.5 3 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...

  • Page 131

    Figure 19-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (V 85 ºC Figure 19-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 2535J–AVR–08/10 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ˚ ...

  • Page 132

    ... Figure 19-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 19.5 Pin Driver Strength Figure 19-19. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V ATtiny13 132 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 60 25 ˚C -40 ˚ ˚ 0.5 1 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ...

  • Page 133

    Figure 19-20. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V Figure 19-21. I/O Pin Source Current vs. Output Voltage (Low Power Ports, V 2535J–AVR–08/10 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS -40 ...

  • Page 134

    ... Figure 19-22. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V Figure 19-23. I/O Pin Sink Current vs. Output Voltage (Low Power Ports ATtiny13 134 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS 0.5 1 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE ...

  • Page 135

    Figure 19-24. I/O Pin Sink Current vs. Output Voltage (Low Power Ports, V Figure 19-25. I/O Pin Source Current vs. Output Voltage (V 2535J–AVR–08/10 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE LOW POWER PORTS, 1. ...

  • Page 136

    ... Figure 19-26. I/O Pin Source Current vs. Output Voltage (V Figure 19-27. I/O Pin Source Current vs. Output Voltage (V ATtiny13 136 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 35 30 -40 ˚C 25 ˚ ˚ 0.5 1 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 10 -40 ˚ ˚ ˚ ...

  • Page 137

    Figure 19-28. I/O Pin Sink Current vs. Output Voltage (V Figure 19-29. I/O Pin Sink Current vs. Output Voltage (V 2535J–AVR–08/10 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 100 ...

  • Page 138

    ... Figure 19-30. I/O Pin Sink Current vs. Output Voltage (V Figure 19-31. Reset Pin as I/O - Source Current vs. Output Voltage (V ATtiny13 138 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.2 0.4 0.6 0.8 V RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 1.6 1.4 -40 ˚C 1.2 25 ˚ ˚C 0.8 0.6 0.4 0 1.8V 1.8V CC -40 ˚C 25 ˚C 85 ˚ ...

  • Page 139

    Figure 19-32. Reset Pin as I/O - Source Current vs. Output Voltage (V Figure 19-33. Reset Pin as I/O - Source Current vs. Output Voltage (V 2535J–AVR–08/10 RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 2.5 -40 ˚C ...

  • Page 140

    ... Figure 19-34. Reset Pin as I/O - Sink Current vs. Output Voltage (V Figure 19-35. Reset Pin as I/O - Sink Current vs. Output Voltage (V ATtiny13 140 RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE 0 RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE V 4.5 4 3.5 3 2.5 2 1 -40 ˚C 25 ˚ ...

  • Page 141

    Figure 19-36. Reset Pin as I/O - Sink Current vs. Output Voltage (V 19.6 Pin Thresholds and Hysteresis Figure 19-37. I/O Pin Input Threshold Voltage vs. V 2535J–AVR–08/10 RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE 1.6 1.4 ...

  • Page 142

    ... Figure 19-38. I/O Pin Input Threshold Voltage vs. V Figure 19-39. I/O Pin Input Hysteresis vs. V ATtiny13 142 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 3 2.5 2 1.5 1 0.5 0 1 I/O PIN INPUT HYSTERESIS vs. V 0.45 0.4 -40 ºC 0.35 0.3 25 ºC 0.25 0.2 85 ºC 0.15 0.1 0.05 0 1.5 2 2.5 3 (VIL, I/O Pin Read as '0 3 ...

  • Page 143

    Figure 19-40. Reset Pin as I/O - Input Threshold Voltage vs. V Figure 19-41. Reset Pin as I/O - Input Threshold Voltage vs. V 2535J–AVR–08/10 RESET PIN AS I/O - THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' ...

  • Page 144

    ... Figure 19-42. Reset Pin as I/O - Pin Hysteresis vs. V Figure 19-43. Reset Input Threshold Voltage vs. V ATtiny13 144 RESET PIN PIN HYSTERESIS vs. V 0.7 0.6 -40 ºC 0.5 25 ºC 0.4 85 ºC 0.3 0.2 0.1 0 1 RESET INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' 2.5 2 1.5 -40 ˚ ˚C 25 ˚C 0.5 0 1 ...

  • Page 145

    Figure 19-44. Reset Input Threshold Voltage vs. V Figure 19-45. Reset Input Pin Hysteresis vs. V 2535J–AVR–08/10 RESET INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 2 ˚C 25 ˚C 0.5 -40 ˚C ...

  • Page 146

    ... BOD Thresholds and Analog Comparator Offset Figure 19-46. BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) Figure 19-47. BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) ATtiny13 146 BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3 4.5 4.4 4.3 4.2 -60 -40 -20 0 Temperature (C) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7 2.9 2.8 2.7 2.6 -60 -40 -20 0 Temperature (C) V Rising V CC Falling 100 V Rising V ...

  • Page 147

    Figure 19-48. BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) Figure 19-49. Bandgap Voltage vs. V 2535J–AVR–08/10 BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8 1.9 1.85 1.8 1.75 -60 -40 -20 0 Temperature (C) CC BANDGAP VOLTAGE vs. V 1.06 1.04 ...

  • Page 148

    ... Internal Oscillator Speed Figure 19-50. Calibrated 9.6 MHz RC Oscillator Frequency vs. Temperature Figure 19-51. Calibrated 9.6 MHz RC Oscillator Frequency vs. V ATtiny13 148 CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 10.3 10.1 9.9 9.7 9.5 5.5 V 9.3 4.5 V 9.1 2.7 V 8.9 1.8 V 8.7 8.5 -60 -40 -20 0 Temperature (C) CALIBRATED 9.6 MHz RC OSCILLATOR FREQUENCY vs 10.5 10 9.5 9 8.5 8 1 100 CC CC 3 ˚ ...

  • Page 149

    Figure 19-52. Calibrated 9.6 MHz RC Oscillator Frequency vs. Osccal Value Figure 19-53. Calibrated 4.8 MHz RC Oscillator Frequency vs. Temperature 2535J–AVR–08/10 CALIBRATED 9.6MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE ...

  • Page 150

    ... Figure 19-54. Calibrated 4.8 MHz RC Oscillator Frequency vs. V Figure 19-55. Calibrated 4.8 MHz RC Oscillator Frequency vs. Osccal Value ATtiny13 150 CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. V 5.2 5 4.8 4.6 4.4 1 CALIBRATED 4.8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE OSCCAL VALUE CC CC 3.5 4 4.5 5 5.5 (V) ...

  • Page 151

    Figure 19-56. 128 kHz Watchdog Oscillator Frequency vs. V Figure 19-57. 128 kHz Watchdog Oscillator Frequency vs. Temperature 2535J–AVR–08/10 128 kHz WATCHDOG OSCILLATOR FREQUENCY vs. V 120 115 110 105 100 1.5 2 2.5 3 128 kHz WATCHDOG OSCILLATOR FREQUENCY ...

  • Page 152

    ... Current Consumption of Peripheral Units Figure 19-58. Brownout Detector Current vs. V Figure 19-59. ADC Current vs. V ATtiny13 152 BROWNOUT DETECTOR CURRENT vs 1 ADC CURRENT vs. V 350 300 250 200 150 100 50 0 1 3 3.5 4 4.5 5 (V) CC -40 ˚ ...

  • Page 153

    Figure 19-60. Analog Comparator Current vs. V Figure 19-61. Programming Current vs. V 2535J–AVR–08/10 ANALOG COMPARATOR CURRENT vs. V 140 120 100 1 PROGRAMMING CURRENT vs. Vcc 4 3.5 3 2.5 ...

  • Page 154

    ... Current Consumption in Reset and Reset Pulse width Figure 19-62. Reset Supply Current vs. V Figure 19-63. Reset Supply Current vs. V ATtiny13 154 CC Reset Pull-up) RESET SUPPLY CURRENT vs. V 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 0.14 0.12 0.1 0.08 0.06 0.04 0. 0.1 0.2 0.3 0.4 Frequency (MHz) CC Pull-up) RESET SUPPLY CURRENT vs MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 3 ...

  • Page 155

    Figure 19-64. Reset Pulse Width vs. V 2535J–AVR–08/10 CC RESET PULSE WIDTH vs. V 2500 2000 1500 1000 500 0 1.8 2.1 2.5 2 3.3 3.5 4 4.5 5 5 ºC 25 ºC -40 ...

  • Page 156

    ... ACSR ACD 0x07 ADMUX – 0x06 ADCSRA ADEN 0x05 ADCH 0x04 ADCL 0x03 ADCSRB – 0x02 Reserved 0x01 Reserved 0x00 Reserved ATtiny13 156 Bit 6 Bit 5 Bit 4 Bit – – – – SP[7:0] – INT0 PCIE – – INTF0 PCIF – ...

  • Page 157

    Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI ...

  • Page 158

    ... SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ATtiny13 158 Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word ...

  • Page 159

    Mnemonics Operands ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV Rd, Rr ...

  • Page 160

    ... ATtiny13V-10SSU S8S1 ATtiny13V-10SSUR S8S1 ATtiny13V-10MU 20M1 ATtiny13V-10MUR 20M1 ATtiny13V-10MMU 10M1 ATtiny13V-10MMUR 10M1 ATtiny13-20PU 8P3 ATtiny13-20SU 8S2 ATtiny13-20SUR 8S2 ATtiny13-20SSU S8S1 ATtiny13-20SSUR S8S1 ATtiny13-20MU 20M1 ATtiny13-20MUR 20M1 ATtiny13-20MMU 10M1 ATtiny13-20MMUR 10M1 117. Package Type (2) Operation Range Industrial (1) (-40°C to +85°C) ...

  • Page 161

    Packaging Information 23.1 8P3 Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...

  • Page 162

    ... Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com ATtiny13 162 TOP VIEW ...

  • Page 163

    S8S1 3 Top View e D Side View End View Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 2325 Orchard Parkway San Jose, CA 95131 ...

  • Page 164

    ... D2 Pin #1 Notch (0. BOTTOM VIEW Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. Note: 2325 Orchard Parkway San Jose, CA 95131 R ATtiny13 164 TITLE 20M1, 20-pad 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) ...

  • Page 165

    Pin TOP VIEW E1 L BOTTOM VIEW Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5. 2. The terminal # Lasser-marked Feature. 2325 Orchard Parkway San Jose, CA 95131 R ...

  • Page 166

    ... Errata The revision letter in this section refers to the revision of the ATtiny13 device. 24.1 ATtiny13 Rev. D • EEPROM can not be written below 1.9 Volt 1. EEPROM can not be written below 1.9 Volt Writing the EEPROM at V Problem Fix/Workaround Do not write the EEPROM when V 24.2 ATtiny13 Rev. C Revision C has not been sampled. ...

  • Page 167

    ... This is done by selecting a long enough time-out period. 24.3.6 EEPROM can not be written below 1.9 Volt Writing the EEPROM at V Problem Fix/Workaround Do not write the EEPROM when V 24.4 ATtiny13 Rev. A Revision A has not been sampled. 2535J–AVR–08/10 (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. below 1.9 volts might fail below 1 ...

  • Page 168

    ... Moved Tables: – – – 9. Updated Register Description for Sections: ATtiny13 168 “Ordering Information” on page “Features” on page 1. “Calibrated Internal RC Oscillator Accuracy” on page 118 “Analog Comparator Characteristics” on page 119 “System Clock and Clock Options” on page 23 “ ...

  • Page 169

    ... Information” on page Updated “Packaging Information” on page Revision not published. Bits EEMWE/EEWE changed to EEMPE/EEPE in document. Updated “Pinout ATtiny13/ATtiny13V” on page Updated “Write Fuse Low Bits” in Added “Pin Change Interrupt Timing” on page Updated “GIMSK – General Interrupt Mask Register” on page Updated “ ...

  • Page 170

    ... Rev. 2535A-06/03 1. ATtiny13 170 Updated “DC Characteristics” on page Updated “Typical Characteristics” on page Updated “Ordering Information” on page Updated “Packaging Information” on page Updated “Errata” on page 166. Maximum Speed Grades changed: 12MHz to 10MHz, 24MHz to 20MHz Updated “ ...

  • Page 171

    Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 4 3 General Information ................................................................................. 6 4 CPU Core .................................................................................................. 7 5 Memories ................................................................................................ 15 6 System Clock and Clock Options ......................................................... 23 7 Power Management ...

  • Page 172

    ... System Control and Reset .................................................................... 34 9 Interrupts ................................................................................................ 44 10 I/O Ports .................................................................................................. 48 11 8-bit Timer/Counter0 with PWM ............................................................ 58 12 Timer/Counter Prescaler ....................................................................... 76 13 Analog Comparator ............................................................................... 78 14 Analog to Digital Converter .................................................................. 81 ATtiny13 ii 7.3 Register Description ........................................................................................32 8.1 Reset Sources .................................................................................................35 8.2 Internal Voltage Reference ..............................................................................37 8.3 Watchdog Timer ..............................................................................................37 8.4 Register Description ........................................................................................41 9.1 Interrupt Vectors ..............................................................................................44 9.2 External Interrupts ...........................................................................................45 9.3 Register Description ........................................................................................46 10 ...

  • Page 173

    On-chip Debug System .................................................... 95 16 Self-Programming the Flash ................................................................. 97 17 Memory Programming ......................................................................... 102 2535J–AVR–08/10 14.1 Features ..........................................................................................................81 14.2 Overview ..........................................................................................................81 14.3 Operation .........................................................................................................82 14.4 Starting a Conversion ......................................................................................82 14.5 Prescaling and Conversion Timing ..................................................................83 14.6 ...

  • Page 174

    ... Electrical Characteristics .................................................................... 115 19 Typical Characteristics ........................................................................ 123 20 Register Summary ............................................................................... 156 21 Instruction Set Summary .................................................................... 158 22 Ordering Information ........................................................................... 160 23 Packaging Information ........................................................................ 161 24 Errata ..................................................................................................... 166 ATtiny13 iv 17.6 Serial Programming .......................................................................................105 17.7 High-Voltage Serial Programming .................................................................108 17.8 Considerations for Efficient Programming .....................................................112 18.1 Absolute Maximum Ratings* .........................................................................115 18.2 DC Characteristics .........................................................................................115 18.3 Speed Grades ...............................................................................................117 18 ...

  • Page 175

    ... Datasheet Revision History ................................................................ 168 Table of Contents....................................................................................... i 2535J–AVR–08/10 24.1 ATtiny13 Rev. D ............................................................................................166 24.2 ATtiny13 Rev. C ............................................................................................166 24.3 ATtiny13 Rev. B .............................................................................................166 24.4 ATtiny13 Rev. A .............................................................................................167 25.1 Rev. 2535J-08/10 ..........................................................................................168 25.2 Rev. 2535I-05/08 ...........................................................................................168 25.3 Rev. 2535H-10/07 .........................................................................................169 25.4 Rev. 2535G-01/07 .........................................................................................169 25.5 Rev. 2535F-04/06 ..........................................................................................169 25.6 Rev. 2535E-10/04 ..........................................................................................169 25.7 Rev. 2535D-04/04 .........................................................................................170 25 ...

  • Page 176

    ... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Unit 1-5 & ...