ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 77

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ATtiny13

Manufacturer Part Number
ATtiny13
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny13

Flash (kbytes)
1 Kbytes
Pin Count
8
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
6
Ext Interrupts
6
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.06
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
Output Compare Channels
2
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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12.4
12.4.1
2535J–AVR–08/10
Register Description.
GTCCR – General Timer/Counter Control Register
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 12-2. Prescaler for Timer/Counter0
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by
hardware, and the Timer/Counter start counting.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
PSR10
Bit
Read/Write
Initial Value
clk
T0
I/O
1. The synchronization logic on the input pins (
Synchronization
TSM
R/W
7
0
R
6
0
Clear
R
5
0
R
4
0
T0)
R
is shown in
3
0
R
2
0
Figure 12-1 on page
clk
R
1
0
T0
PSR10
R/W
clk_I/O
0
0
76.
/2.5.
GTCCR
77

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