ATtiny13 Atmel Corporation, ATtiny13 Datasheet - Page 99

• Manufacturer Part Number: ATtiny13
• Manufacturer: Atmel Corporation

Specifications of ATtiny13

• Flash (kbytes): 1 Kbytes
• Pin Count: 8
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 6
• Ext Interrupts: 6
• Usb Speed: No
• Usb Interface: No
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.06
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 2
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.5
16.6
16.6.1
16.6.2
2535J–AVR–08/10
EEPROM Write Prevents Writing to SPMCSR
Reading Fuse and Lock Bits from Firmware
Reading Lock Bits from Firmware
Reading Fuse Bits from Firmware
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the
Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
fuses and lock bits from software will also be prevented during the EEPROM write operation. It is
recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that
the bit is cleared before writing to the SPMCSR Register.
It is possible to read fuse and lock bits from software.
Issuing an LPM instruction within three CPU cycles after RFLB and SELFPRGEN bits have
been set in SPMCSR will return lock bit values in the destination register. The RFLB and SELF-
PRGEN bits automatically clear upon completion of reading the lock bits, or if no LPM instruction
is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles.
When RFLB and SELFPRGEN are cleared, LPM functions normally.
To read the lock bits, follow the below procedure.
If successful, the contents of the destination register are as follows.
See section
bits.
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,
only the addresses are different.
To read the Fuse Low Byte (FLB), follow the below procedure:
If successful, the contents of the destination register are as follows.
Bit
Rd
Bit
Rd
1. Load the Z-pointer with 0x0001.
2. Set RFLB and SELFPRGEN bits in SPMCSR.
3. Issuing an LPM instruction within three clock cycles will return lock bits in the destina-
1. Load the Z-pointer with 0x0000.
2. Set RFLB and SELFPRGEN bits in SPMCSR.
3. Issuing an LPM instruction within three clock cycles will FLB in the destination register.
tion register.
“Program And Data Memory Lock Bits” on page 102
FLB7
7
–
7
FLB6
6
–
6
FLB5
5
–
5
FLB4
4
–
4
FLB3
3
–
3
FLB2
2
–
2
for more information on lock
FLB1
LB2
1
1
FLB0
LB1
0
0
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