ATtiny167 Atmel Corporation, ATtiny167 Datasheet
ATtiny167
Specifications of ATtiny167
Available stocks
Related parts for ATtiny167
ATtiny167 Summary of contents
Page 1
... ATtiny87/167 • Speed Grade: – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 8 MHz @ 2.7 – 5.5V – 0 – 16 MHz @ 4.5 – 5.5V • Industrial Temperature Range ® 8-bit Microcontroller 8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller ATtiny87 ATtiny167 Preliminary Rev. 8265B–AVR–09/10 ...
Page 2
... Description 1.1 Comparison Between ATtiny87 and ATtiny167 ATtiny87 and ATtiny167 are hardware and software compatible. They differ only in memory sizes as shown in Table 1-1. Device ATtiny167 ATtiny87 1.2 Part Description The ATtiny87/167 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny87/167 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed ...
Page 3
Block Diagram Figure 1-1. 8265B–AVR–09/10 Block Diagram Watchdog Power Timer Supervision POR / BOD & Watchdog RESET Oscillator Oscillator Flash Circuits / Clock Generation EEPROM Timer/Counter-1 Timer/Counter-0 SPI & USI Analog Comp. PORT B (8) PORT A (8) PB[0:7] ...
Page 4
... SDA / DI / ICP1 / ADC4 / PCINT4) PA4 (SCK / SCL / USCK / T1 / ADC5 / PCINT5) PA5 (SS / AIN0 / ADC6 / PCINT6) PA6 (AREF / XREF / AIN1 / ADC7 / PCINT7) PA7 Figure 1-3. Pinout ATtiny87/167 - QFN32/MLF32 (INT1 / ISRC / ADC3 / PCINT3) PA3 ATtiny87/ATtiny167 4 PB0 (PCINT8 / OC1AU / DI / SDA PB1 (PCINT9 / OC1BU / DO) ...
Page 5
Pin Description 1.5.1 VCC Supply voltage. 1.5.2 GND Ground. 1.5.3 AVCC Analog supply voltage. 1.5.4 AGND Analog ground. 1.5.5 Port A (PA7:PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The ...
Page 6
... PPM over 20 years at 85°C or 100 years at 25°C. 1.9 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device has been characterized. ATtiny87/ATtiny167 6 8265B–AVR–09/10 ...
Page 7
AVR CPU Core 2.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access mem- ories, perform calculations, ...
Page 8
... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny87/ATtiny167 8 8265B–AVR–09/10 ...
Page 9
SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the ...
Page 10
... The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indi- rect address registers X, Y, and Z are defined as described in ATtiny87/ATtiny167 10 shows the structure of the 32 general purpose working registers in the CPU. ...
Page 11
Figure 2-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displace- ment, automatic increment, and automatic decrement (see the instruction set reference for details). 2.5 Stack Pointer The Stack is mainly used for ...
Page 12
... The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. ATtiny87/ATtiny167 12 , directly generated from the selected clock source for ...
Page 13
Interrupt behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt ...
Page 14
... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny87/ATtiny167 14 ; set Global Interrupt Enable ; enter sleep, waiting for interrupt /* set Global Interrupt Enable */ 8265B– ...
Page 15
... ISRAM size 512 bytes ISRAM start 0x0100 ISRAM end 0x02FF E2 size 512 bytes - 0x0000 E2 end 0x01FF 15). Since all AVR instructions are bits Section 20.2.1 “SPMCSR – Store Program for more details. Section 21. “Memory Pro- ATtiny167 16 K bytes 0x3FFF (1) 0x1FFF (2) 15 ...
Page 16
... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers and the internal data SRAM in the ATtiny87/167 are all accessible through all these addressing modes. The Register File is described in ATtiny87/ATtiny167 16 12. Program Memory Map Program Memory shows how the ATtiny87/167 SRAM Memory is organized ...
Page 17
Figure 3-2. 3.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 3-3. 3.3 EEPROM Data Memory The ATtiny87/167 contains EEPROM memory ...
Page 18
... If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming not possible to do any other EEPROM operations. ATtiny87/ATtiny167 18 is likely to rise or fall slowly on Power-up/down. This causes the device for some CC “ ...
Page 19
The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre- quency is within the requirements described in page The following code examples show one assembly and one C function for erase, write, or atomic write ...
Page 20
... Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V ATtiny87/ATtiny167 20 ; Wait for completion of previous write ...
Page 21
If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3.4 I/O Memory The I/O space definition of the ATtiny87/167 ...
Page 22
... Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming. ATtiny87/ATtiny167 ...
Page 23
Bit 2 – EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not. When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected ...
Page 24
... Figure 4-1. Asynchronous Timer/Counter0 ATtiny87/ATtiny167 24 presents the principal clock systems in the AVR and their distribution. All of the and “Dynamic Clock Switch” on page Clock Distribution ...
Page 25
CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with the AVR core operation. Exam- ples of such modules are the General Purpose Register File, the Status Register and the Data memory ...
Page 26
... The Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out even when this Oscillator is used as the device clock. For more information on the pre-pro- grammed calibration value, see the section ATtiny87/ATtiny167 26 Table 4-2. Number of Watchdog Oscillator Cycles = 5 ...
Page 27
Table 4-3. Notes: When this Oscillator is selected, start-up times are determined by the SUT Fuses or by CSUT field as shown in Table 4-4. SUT[1:0] CSUT[1:0] Notes: 4.2.3 128 KHz Internal Oscillator The 128 KHz internal Oscillator is a ...
Page 28
... The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by CKSEL[3:1] fuses or by CSEL[3:1] field as shown in Table Table 4-6. CKSEL[3:1] CSEL[3:1] Notes: ATtiny87/ATtiny167 28 Table 4-6. For ceramic resonators, the capacitor values given Crystal Oscillator Connections C2 C1 4-6 ...
Page 29
The CKSEL0 Fuse together with the SUT[1:0] Fuses or CSEL0 together with CSUT[1:0] field select the start-up times as shown in Table 4-7. CKSEL0 CSEL0 Notes: 4.2.5 Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock ...
Page 30
... When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as shown in This external clock can be used by the asynchronous timer if the high or low frequency Crystal Oscillator is not running timer is then able to enable this input. ATtiny87/ATtiny167 30 Low-frequency Crystal Oscillator Connections C1=12-22 pF 32.768 KHz ...
Page 31
Table 4-9. SUT[1:0] CSUT[1:0] Notes: Note that the System Clock Prescaler can be used to implement run-time changes of the inter- nal clock frequency while still ensuring stable operation. Refer to page 37 4.2.7 Clock Output Buffer If not using ...
Page 32
... CLKSELR register. CSEL[3:0] will select the clock source and CSUT[1:0] will select the start-up time (just as CKSEL and SUT fuse bits do sure that a clock source is operating, the ‘Request for Clock Availability ’ command must be executed after the ‘Enable ATtiny87/ATtiny167 32 – ‘Recover System Clock Source’, – ...
Page 33
Clock Source’ command. This will indicate via the CLKRDY bit in the CLKCSR register that a valid clock source is available and operational. The ‘Disable Clock Source’ command disables the clock source indicated by the settings of CLKSELR register (only ...
Page 34
... Moreover, the enables of the external clock and of the external low-frequency oscillator are shared with the asynchronous timer. 4.3.8 Clock Monitoring A safe system needs to monitor its clock sources. Two domains need to be monitored: - Clock sources for peripherals, - Clocks sources for system clock generation. ATtiny87/ATtiny167 34 _ RECOVER 0x05 _ ENABLE ...
Page 35
In the first domain, the user (code) can easily check the validity of the clock(s) Command” on page In the second domain, the lack of a clock results in the code not running. Thus, the presence of the system clock ...
Page 36
... Here is a “light” C-code of a clock switching function using automatic clock monitoring. C Code Example void ClockSwiching (unsigned char clk #define CLOCK #define CLOCK #define CLOCK #define CLOCK #define WD #define WD unsigned char previous } } ATtiny87/ATtiny167 36 _ RECOVER 0x05 _ ENABLE 0x02 _ SWITCH 0x04 _ ...
Page 37
System Clock Prescaler 4.4.1 Features The ATtiny87/167 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can ...
Page 38
... Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. ATtiny87/ATtiny167 CLKPCE – ...
Page 39
Table 4-10. CLKPS3 4.5.3 CLKCSR – Clock Control & Status Register Bit (0x62) Read/Write Initial Value • Bit 7 – CLKCCE: Clock Control Change Enable The CLKCCE bit must be written to logic one to enable change of the CLKCSR ...
Page 40
... The COUT bit is initialized with ~(CKOUT) Fuse bit. The COUT bit is only used in case of ‘CKOUT’ command. Refer to Buffer” on page 31 In case of ‘Recover System Clock Source’ command, COUT it is not affected (no recovering of this setting). ATtiny87/ATtiny167 40 39.). CLKCSR to zero. bit. ...
Page 41
Bits 5:4 – CSUT[1:0]: Clock Start-up Time CSUT bits are initialized with the values of SUT Fuse bits. In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock start-up time. Refer to subdivisions of ...
Page 42
... SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. ATtiny87/ATtiny167 42 “BOD Disable” on page 43 for more details ...
Page 43
BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, 226, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software for ...
Page 44
... PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. ATtiny87/ATtiny167 44 for details. Section 4.2 “Clock Sources” on page ...
Page 45
Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...
Page 46
... These bits are reserved bits in the ATtiny87/167 and will always read as zero. • Bits 2:1 – SM[1:0]: Sleep Mode Select Bits 1 and 0 These bits select between the four available sleep modes as shown in ATtiny87/ATtiny167 46 Section 6.3 “Watchdog Timer” on page 53 ) and the ADC clock (clk ...
Page 47
Table 5-2. • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode ...
Page 48
... Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. ATtiny87/ATtiny167 48 8265B–AVR–09/10 ...
Page 49
System Control and Reset 6.1 Reset 6.1.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be ...
Page 50
... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V delay, when V Figure 6-2. TIME-OUT INTERNAL RESET ATtiny87/ATtiny167 50 Reset Circuit Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor ...
Page 51
Figure 6-3. TIME-OUT INTERNAL 6.1.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see not running. Shorter pulses are not guaranteed to generate a reset. ...
Page 52
... This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. ATtiny87/ATtiny167 52 Brown-out Reset During Operation V CC ...
Page 53
Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 0 – PORF: Power-on ...
Page 54
... WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. ATtiny87/ATtiny167 54 Watchdog Timer WATCHDOG ...
Page 55
The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occur during the execution of ...
Page 56
... Notes: 6.3.2 Clock monitoring The Watchdog Timer can be used to detect a loss of system clock. This configuration is driven by the dynamic clock switch circuit. Please refer to 34 for more information. ATtiny87/ATtiny167 56 (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCR ori r16, (1< ...
Page 57
WDTCR – Watchdog Timer Control Register Bit (0x60) Read/Write Initial Value • Bit 7 – WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con- figured for ...
Page 58
... The different prescaling values and their corresponding time-out periods are shown in 6-2 on page Table 6-2. WDP3 ATtiny87/ATtiny167 58 58. Watchdog Timer Prescale Select WDP2 WDP1 WDP0 WDT Oscillator Cycles (2048) cycles (4096) cycles (8192) cycles ...
Page 59
... This section describes the specifics of the interrupt handling as performed in ATtiny87/167. For a general explanation of the AVR interrupt handling, refer to dling” on page 7.1 Interrupt Vectors in ATtiny87/167 Table 7-1. Reset and Interrupt Vectors in ATtiny87/167 Program Address Vector Nb. ATtiny87 ATtiny167 1 0x0000 0x0000 2 0x0001 0x0002 3 0x0002 0x0004 4 ...
Page 60
... RESET: 0x0015 0x0016 0x0017 0x0018 0x0019 Note: ATtiny87/ATtiny167 60 (Note:) Label Code rjmp RESET rjmp INT0addr rjmp INT1addr rjmp PCINT0addr rjmp PCINT1addr rjmp WDTaddr rjmp ICP1addr rjmp OC1Aaddr ...
Page 61
... Program Setup in ATtiny167 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny167 is (4-byte step - using “jmp” instruction): Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E ...
Page 62
... The start-up time is defined by the SUT and CKSEL Fuses as described in 8.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 8-1. ATtiny87/ATtiny167 62 24. Low level interrupts and the edge interrupt on INT0 or INT1 are detected “Clock Systems and their Distribution” on page Timing of pin change interrupts pin_lat ...
Page 63
Register Description 8.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved ...
Page 64
... PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bits 7:2 – Res: Reserved Bits These bits are reserved bits in the ATtiny87/167 and will always read as zero. • Bit 1 – PCIE1: Pin Change Interrupt Enable 1 ATtiny87/ATtiny167 – – ...
Page 65
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT[15:8] pin will cause an inter- rupt. The corresponding interrupt of ...
Page 66
... Bit 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0 Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny87/ATtiny167 66 8265B–AVR–09/10 ...
Page 67
I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
Page 68
... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATtiny87/ATtiny167 68 (Note:) General Digital I/O ...
Page 69
Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port. 9.2.3 Break-Before-Make ...
Page 70
... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. ATtiny87/ATtiny167 70 summarizes the control signals for the pin value. Port Pin Configurations ...
Page 71
Figure 9-5. The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and ...
Page 72
... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. ATtiny87/ATtiny167 72 Figure 9-2, the digital input signal can be clamped to ground at the input of the “ ...
Page 73
Figure 9-6. Pxn Note: 8265B–AVR–09/10 (1) Alternate Port Functions PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 0 DIEOExn DIEOVxn 1 SLEEP 0 PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION ...
Page 74
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for fur- ther details. ATtiny87/ATtiny167 74 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables ...
Page 75
MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn ...
Page 76
... Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 9-3. Port Pin ATtiny87/ATtiny167 76 Port A Pins Alternate Functions Alternate Function PCINT7 (Pin Change Interrupt 7) ADC7 (ADC Input Channel 7) PA7 AIN1 (Analog Comparator Positive Input) XREF (Internal Voltage Reference Output) AREF (External Voltage Reference Input) ...
Page 77
The alternate pin configuration is as follows: • Port A, Bit 7 – PCINT7/ADC7/AIN1/XREF/AREF • PCINT7: Pin Change Interrupt, source 7. • ADC7: Analog to Digital Converter, channel 7. • AIN1: Analog Comparator Positive Input. This pin is directly connected ...
Page 78
... PORTA0 will turn on the internal pull-up. • RXLIN: LIN Receive pin. When the LIN is enabled, this pin is configured as an input regardless of the value of DDA0. When the pin is forced input, a logical one in PORTA0 will turn on the internal pull-up. ATtiny87/ATtiny167 78 one ) to serve these functions. ...
Page 79
Table 9-4 in Figure 9-6 on page Table 9-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8265B–AVR–09/10 and Table 9-5 relate the alternate functions of Port A to the overriding signals shown 73. Overriding ...
Page 80
... Table 9-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny87/ATtiny167 80 Overriding Signals for Alternate Functions in PA[3:0] PA3/PCINT3/ADC3/ PA2/PCINT2/ADC2/ ISRC/INT1 OC0A/DO/MISO 0 SPE & MSTR PORTA3 & PUD PORTA2 & PUD 0 SPE & MSTR 0 0 (SPE & MSTR) | (USI_2_WIRE & ...
Page 81
Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-6. Port Pin The alternate pin configuration is as follows: • Port B, Bit 7 – PCINT15/ADC10/OC1BX/RESET/dW • PCINT15: Pin Change Interrupt, source ...
Page 82
... CLKI: External clock input. When used as a clock pin, the pin can not be used as an I/O pin. Note: • Port B, Bit 3 – PCINT11/OC1BV • PCINT11: Pin Change Interrupt, source 11. ATtiny87/ATtiny167 82 If PB4 is used as a clock pin (XTAL1 or CLKI), DDB4, PORTB4 and PINB4 will all read 0. 8265B–AVR–09/10 ...
Page 83
OC1BV: Output Compare and PWM Output B-V for Timer/Counter1. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1BV pin is also the output pin for the PWM mode timer ...
Page 84
... Table 9-7 in Figure 9-6 on page Table 9-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny87/ATtiny167 84 and Table 9-8 relate the alternate functions of Port B to the overriding signals shown 73. Overriding Signals for Alternate Functions in PB[7:4] PB7/PCINT15/ ADC10/OC1BX/ PB6/PCINT14/ RESET/dW ADC9/OC1AX/INT0 ...
Page 85
Table 9-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8265B–AVR–09/10 Overriding Signals for Alternate Functions in PB[3:0] PB3/PCINT11/ PB2/PCINT10/ OC1BV OC1AV/USCK/SCL (USI_2_WIRE & 0 USIPOS) (USI_SCL_HOLD | 0 PORTB2) & ...
Page 86
... PORTB – Port B Data Register Bit 0x05 (0x25) Read/Write Initial Value 9.4.5 DDRB – Port B Data Direction Register Bit 0x04 (0x24) Read/Write Initial Value 9.4.6 PINB – Port B Input Pins Register Bit 0x03 (0x23) Read/Write Initial Value ATtiny87/ATtiny167 PORTA7 PORTA6 PORTA5 PORTA4 R/W R/W R/W R ...
Page 87
Timer/Counter0 and Asynchronous Operation Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 10.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width ...
Page 88
... The result of the compare can be used by the Waveform Generator to gen- erate a PWM or variable frequency output on the Output Compare pin (OC0A). Compare Unit” on page 90. flag (OCF0A) which can be used to generate an Output Compare interrupt request. ATtiny87/ATtiny167 88 TCCRnx count clear ...
Page 89
Definitions The following definitions are used extensively throughout the section: BOTTOM MAX TOP 10.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source is selected by the ...
Page 90
... Compare Output mode (COM0A[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation Figure 10-3 Figure 10-3. Output Compare Unit, Block Diagram ATtiny87/ATtiny167 90 0). clk 0 can be generated from an external or internal clock present or not ...
Page 91
The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of ...
Page 92
... Waveform Generation mode bits do. The COM0A[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0A[1:0] bits control whether the output should be set, cleared, or toggled at a compare match ATtiny87/ATtiny167 92 COMnx1 Waveform ...
Page 93
For detailed timing information refer to 10.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM0[1:0] = 0). In this mode the count- ing direction is always up (incrementing), and no counter clear is performed. The counter ...
Page 94
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent com- pare matches between OCR0A and TCNT0. Figure 10-6. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period ATtiny87/ATtiny167 ------------------------------------------------- - OCnx ⋅ ...
Page 95
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of ...
Page 96
... PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. ATtiny87/ATtiny167 96 1 ...
Page 97
Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk 0) is therefore shown as a clock enable signal. In asynchronous mode, clk T replaced by the Timer/Counter Oscillator clock. The figures ...
Page 98
... MCU will not wake up. • If Timer/Counter0 is used to wake the device up from Power-save mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one ATtiny87/ATtiny167 98 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Prescaler (f ...
Page 99
TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether ...
Page 100
... These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0] bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is con- nected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0A pin must be set in order to enable the output driver. ATtiny87/ATtiny167 100 clk I/O ...
Page 101
When OC0A is connected to the pin, the function of the COM0A[1:0] bits depends on the WGM0[1:0] bit setting. WGM0[1:0] bits are set to a normal or CTC mode (non-PWM). Table 10-1. COM0A1 Table 10-2 PWM mode. Table 10-2. COM0A1 ...
Page 102
... A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. • Bits 6:3 – Res: Reserved Bits These bits are reserved in the ATtiny87/167 and will always read as zero. • Bits 2:0 – CS0[2:0]: Clock Select ATtiny87/ATtiny167 102 92.). Waveform Generation Mode Bit Description WGM01 WGM00 ...
Page 103
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table Table 10-5. CS02 10.11.3 TCNT0 – Timer/Counter0 Register Bit 0x27 (0x47) Read/Write Initial Value The Timer/Counter Register gives direct access, both for read ...
Page 104
... The mechanisms for reading TCNT0, OCR0A, TCCR0A and TCCR0B are different. When reading TCNT0, the actual timer value is read. When reading OCR0A, TCCR0A or TCCR0B the value in the temporary storage register is read. ATtiny87/ATtiny167 104 29.) or from external clock on XTAL1 pin 30.) depending on EXCLK setting. When the value of AS0 is ...
Page 105
TIMSK0 – Timer/Counter0 Interrupt Mask Register Bit (0x6E) Read/Write Initial Value • Bits 7:2 – Res: Reserved Bits These bits are reserved in the ATtiny87/167 and will always read as zero. • Bit 1 – OCIE0A: Timer/Counter0 Output Compare ...
Page 106
... If the bit is written when Timer/Counter0 is operating in asynchro- nous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the Timer/Counter Synchronization Mode” on page 109 Synchronization mode. ATtiny87/ATtiny167 106 ...
Page 107
Timer/Counter1 Prescaler 11.1 Overview Most bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number. 11.1.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting ...
Page 108
... Oscillator source (crystal, resonator, and capaci- tors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Figure 11-2. Prescaler for Timer/Counter1 Note: ATtiny87/ATtiny167 108 < f /2) given a 50/50 % duty cycle. Since the edge detec- ExtClk clk_I/O /2 ...
Page 109
Register Description 11.2.1 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value ...
Page 110
... X. However, when using the register or bit defines in a program, the precise form must be used. A simplified block diagram of the 16-bit Timer/Counter is shown in placement of I/O pins, refer to including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the ATtiny87/ATtiny167 110 “Pin Configuration” on page “Register Description” on page 132. Figure 12-1 ...
Page 111
Figure 12-1. 16-bit Timer/Counter1 Block Diagram Note: 12.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Reg- ister (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described ...
Page 112
... Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. ATtiny87/ATtiny167 112 ). T n 119 ...
Page 113
Code Examples The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for access- ing the OCR1A/B and ICR1 Registers. Note that ...
Page 114
... Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: C Code Example unsigned int TIM16_ReadTCNT1(void Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATtiny87/ATtiny167 114 (1) ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 ...
Page 115
The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The ...
Page 116
... TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1A/B. For more details about advanced counting sequences and waveform generation, see 122. ATtiny87/ATtiny167 116 shows a block diagram of the counter and its surroundings. DATA BUS ...
Page 117
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM1[3:0] bits. TOV1 can be used for generating a CPU interrupt. 12.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
Page 118
... Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). ATtiny87/ATtiny167 118 112. (Figure 11-1 on page “ ...
Page 119
Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1A/B). If TCNT equals OCR1A/B the comparator signals a match. A match will set the Output Compare Flag (OCF1A/B) at the next timer clock cycle. ...
Page 120
... The Compare Output mode (COM1A/B[1:0]) bits have two functions. The Waveform Genera- tor uses the COM1A/B[1:0] bits for defining the Output Compare (OC1A/B) state at the next compare match. Secondly the COM1A/B[1:0] and OCnxi bits control the OC1A/Bi pin output ATtiny87/ATtiny167 120 112. ...
Page 121
OCnxi bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1A/B[1:0] and ...
Page 122
... Output mode (COM1A/B[1:0]) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1A/B[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1A/B[1:0] bits control whether the output should be set, cleared ATtiny87/ATtiny167 122 OCnxi COMnx1 ...
Page 123
COM1A/B[1:0] bits as shown in For detailed timing information refer to 12.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGM1[3:0] = 0). In ...
Page 124
... The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ATtiny87/ATtiny167 124 when OCR1A is set to zero (0x0000) ...
Page 125
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM1[3: 7), the value in ICR1 (WGM1[3:0] = 14), or the value in ...
Page 126
... The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ATtiny87/ATtiny167 126 f clk_I/O ...
Page 127
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM1[3: 3), the value in ICR1 (WGM1[3:0] = 10), or the value ...
Page 128
... The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: ATtiny87/ATtiny167 128 f OCnxPCPWM ...
Page 129
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM1[3:0] = 8), or the value in OCR1A (WGM1[3:0] = 9). The counter has then reached the TOP and ...
Page 130
... OCR1A/B Register is updated with the OCR1A/B buffer value (only for modes utilizing double buffering). of OCF1A/B. Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1A/B, no Prescaling Figure 12-12 ATtiny87/ATtiny167 130 Table on page 133). The actual OC1A/B value will only be visible f ...
Page 131
Figure 12-12. Timer/Counter Timing Diagram, Setting of OCF1A/B, with Prescaler (f Figure 12-13 and frequency correct PWM mode the OCR1A/B Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 ...
Page 132
... When the OC1Ai or OC1Bi is connected to the pin, the function of the COM1A/B[1:0] bits is dependent of the WGM1[3:0] bits setting. when the WGM1[3:0] bits are set to a Normal or a CTC mode (non-PWM). Table 12-1. OC1Ai OC1Bi 0 1 ATtiny87/ATtiny167 132 clk I/O clk Tn (clk /8) I/O ...
Page 133
Table 12-2 fast PWM mode. Table 12-2. OC1Ai OC1Bi Note: Table 12-3 phase correct or the phase and frequency correct, PWM mode. Table 12-3. OC1Ai OC1Bi Note: • Bits 3:2 ...
Page 134
... Note: 1. The CTC1 and PWM1[1:0] bit definition names are obsolete. Use the WGM1[2:0] definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATtiny87/ATtiny167 134 (1) WGM10 Timer/Counter (PWM10) Mode of Operation 0 0 Normal 0 ...
Page 135
TCCR1B – Timer/Counter1 Control Register B Bit (0x81) Read/Write Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input ...
Page 136
... The OC1Bi bits enable the Output Compare pins of Channel B as shown in page 122. • Bits 3:0 – OC1Ai: Output Compare Pin Enable for Channel A The OC1Ai bits enable the Output Compare pins of Channel A as shown in page 122. ATtiny87/ATtiny167 136 FOC1A FOC1B – ...
Page 137
TCNT1H and TCNT1L – Timer/Counter1 Bit (0x85) (0x84) Read/Write Initial Value The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure ...
Page 138
... Bit 0 – TOIE1: Timer/Counter Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vec- tor (See ”Interrupt Vectors in ATtiny87/167” on page located in TIFR1, is set. ATtiny87/ATtiny167 138 R/W ...
Page 139
TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved for future use. • Bit 5 – ICF1: Input Capture Flag This flag is set when ...
Page 140
... End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode Figure 13-1. SPI Block Diagram /2/4/8/16/32/64/128 Note: ATtiny87/ATtiny167 140 (1) clk IO DIVIDER 1. Refer to Figure 1.4 on page 4, and Table 9-3 on page 76 for SPI pin placement. ...
Page 141
The interconnection between Master and Slave CPUs with SPI is shown in system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
Page 142
... SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direc- tion bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB. Assembly Code Example ATtiny87/ATtiny167 142 Table 13-1. For more details on automatic port overrides, refer to 72 ...
Page 143
C Code Example Note: 8265B–AVR–09/10 SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out ...
Page 144
... The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: ATtiny87/ATtiny167 144 (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret ...
Page 145
SS Pin Functionality 13.2.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS)pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by ...
Page 146
... Bits 1:0 – SPR[1:0]: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clk shown in the following table: Table 13-4. ATtiny87/ATtiny167 146 Figure 13-3 and Figure 13-4 ...
Page 147
SPSR – SPI Status Register Bit 0x2D (0x4D) Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is ...
Page 148
... Table 13-5. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 13-3. SPI Transfer Format with CPHA = 0 Figure 13-4. SPI Transfer Format with CPHA = 1 ATtiny87/ATtiny167 148 and Figure 13-4. Data bits are shifted out and latched in on opposite edges of the Table 13-2 and Table 13-3, as done below: ...
Page 149
USI – Universal Serial Interface 14.1 Features • Two-wire Synchronous Data Transfer (Master or Slave) • Three-wire Synchronous Data Transfer (Master or Slave) • Data Received Interrupt • Wakeup from Idle Mode • In Two-wire Mode: Wake-up from All ...
Page 150
... Slave. The two USI Data Register are interconnected in such way that after eight USCK clocks, the data in each register are interchanged. The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. ATtiny87/ATtiny167 150 Bit7 Bit6 ...
Page 151
The clock is generated by the Master device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. Figure 14-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK DO DI ...
Page 152
... The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4): SPITransfer_Fast: ATtiny87/ATtiny167 152 sts USICR,r16 lds ...
Page 153
SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
Page 154
... The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. Figure 14-5. Two-wire Mode, Typical Timing Diagram SDA SCL ATtiny87/ATtiny167 154 Bit7 Bit6 Bit5 Bit4 Bit3 ...
Page 155
Referring to the timing diagram 1. The a start condition is generated by the Master by forcing the SDA low line while the 2. In addition, the start detector will hold the SCL line low after the Master has forced ...
Page 156
... The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges. ATtiny87/ATtiny167 156 7 6 ...
Page 157
Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the USI Data Register. 14.5.2 USIBR – USI Buffer Register Bit (0xBB) Read/Write Initial Value • Bits 7:0 – USID[7:0]: ...
Page 158
... Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM[1:0] and the USI operation is summarized in ATtiny87/ATtiny167 158 7 6 ...
Page 159
Table 14-1. USIWM1 Note: • Bits 3:2 – USICS[1:0]: Clock Source Select These bits set the clock source for the USI Data Register and counter. The data output latch ensures that the output is changed at ...
Page 160
... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detec- tion of when the transfer is done when operating as a master device. ATtiny87/ATtiny167 160 Relations between the USICS[1:0] and USICLK Setting ...
Page 161
USIPP – USI Pin Position Bit (0xBC) Read/Write Initial Value • Bits 7:1 – Res: Reserved Bits These bits are reserved bits in the ATtiny87/167 and always reads as zero. • Bit 0 – USIPOS: USI Pin Position Setting ...
Page 162
... Full Duplex Operation (Independent Serial Receive and Transmit Processes) • Asynchronous Operation • High Resolution Baud Rate Generator • Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames • Data Over-Run and Framing Error Detection ATtiny87/ATtiny167 162 8265B–AVR–09/10 ...
Page 163
LIN Protocol 15.3.1 Master and Slave A LIN cluster consists of one master task and several slave tasks. A master node contains the master task as well as a slave task. All other nodes contain a slave task only. ...
Page 164
... Tx LIN Header function, • Rx LIN Header function, • LIN Response function. These functions mainly use two services: • Rx service, • Tx service. Because these two services are basically UART services, the controller is also able to switch into an UART function. ATtiny87/ATtiny167 164 8265B–AVR–09/10 ...
Page 165
LIN Overview The LIN/UART controller is designed to match as closely as possible to the LIN software appli- cation structure. The LIN software application is developed as independent tasks, several slave tasks and one master task (c.f. forms to ...
Page 166
... LIN/UART Controller Structure Figure 15-4. LIN/UART Controller Block Diagram CLK IO RxD 15.4.4 LIN/UART Command Overview Figure 15-5. LIN/UART Command Dependencies ATtiny87/ATtiny167 166 Prescaler Sample /bit BAUD_RATE Get Byte Frame Time-out RX Synchronization Monitoring Data FIFO Tx Header IDOK Rx Header LIN Abort Automatic Return Recommended DISABLE Way ...
Page 167
Table 15-1. LENA 0 1 15.4.5 Enable / Disable Setting the LENA bit in LINCR register enables the LIN/UART controller. To disable the LIN/UART controller, LENA bit must be written wait states are implemented, so, the disable ...
Page 168
... While the controller is sending or receiving a response, BREAK and SYNCH fields can be detected and the identifier of this new header will be recorded. Of course, specific errors on the previous response will be maintained with this identifier reception. ATtiny87/ATtiny167 168 ’ data with the update of the checksum calculation, n 8265B– ...
Page 169
Handling Data of LIN response A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LIN- SEL register, repeated accesses to the LINDAT register perform data read or data write (c.f. ...
Page 170
... LIN13 bit in LINCR register is used to select the LIN protocol: • LIN13 = 0 (default): LIN 2.1 protocol, • LIN13 = 1: LIN 1.3 protocol. The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic checksum in LIN 1.3). This bit is irrelevant for UART commands. ATtiny87/ATtiny167 170 Table 15-2. Reset of LIN/UART Registers Register Name LIN Control Reg ...
Page 171
Configuration Depending on the mode (LIN or UART), LCONF[1:0] bits of the LINCR register set the control- ler in the following configuration Table 15-3. Mode LIN UART The LIN configuration is independent of the programmed LIN protocol. The listening ...
Page 172
... BREAK is refused. The re-synchronization is done by adjusting LBT[5:0] value to the SYNCH field of the received header (0x55). Then the PROTECTED IDENTIFIER is sampled using the new value of LBT[5:0]. ATtiny87/ATtiny167 172 , the abort command is taken into account at the end of the byte, ...
Page 173
The re-synchronization implemented in the controller tolerates a clock deviation of ± 20% and adjusts the baud rate in a ± 2% range. The new LBT[5:0] value will be used up to the end of the response. Then, the LBT[5:0] ...
Page 174
... The user initializes LTXDL field before setting the Tx Response command, • After setting the Tx Response command, LRXDL is reset by hardware, • LTXDL will remain unchanged during Tx (during busy signal), • LRXDL will count the number of transmitted bytes (during busy signal), ATtiny87/ATtiny167 174 LIDOK st ...
Page 175
If an error occurs, Tx stops, the corresponding error flag is set and LRXDL will give the number of transmitted bytes without error, • error occurs, LTXOK is set after the transmission of the CHECKSUM, LTXDL will ...
Page 176
... After each LIN error, the LIN controller stops its previous activity and returns to its withdrawal mode (LCMD[2:0] = 000 Writing 1 in LERR of LINSIR register resets LERR bit and all the bits of the LINERR register. ATtiny87/ATtiny167 176 178). There are eight flags: 186). A LIN slave application does not distinguish between ...
Page 177
Frame Time Out According to the LIN protocol, a frame time-out error is flagged if: T This feature is implemented in the LIN/UART controller. Figure 15-12. LIN timing and frame time-out T Header BREAK SYNC Field T T Header_Nominal ...
Page 178
... LINERR.3 LINERR.2 LINERR.1 LINERR.0 15.5.14 Message Filtering Message filtering based upon the whole identifier is not implemented. Only a status for frame headers having 0x3C, 0x3D, 0x3E and 0x3F as identifier is available in the LINSIR register. Table 15-4. ATtiny87/ATtiny167 178 n ⎛ ⎛ ⎜ ⎜ ∑ 255 unsigned char ...
Page 179
The LIN protocol says that a message with an identifier from 60 (0x3C (0x3F) uses a classic checksum (sum over the data bytes only). Software will be responsible for switching correctly the LIN13 bit to provide/check this ...
Page 180
... LINBRRH LTXDL3 LTXDL2 LINDLR 0 R/W 0 R/W LP1 LP0 LINIDR — — LINSEL LDATA7 LDATA6 LINDAT 0 R/W 0 R/W ATtiny87/ATtiny167 180 Bit 5 Bit 4 LCONF1 LCONF0 0 R/W 0 R/W LIDST0 LBUSY — — LOVERR LFERR LBT5 LBT4 ...
Page 181
LINCR – LIN Control Register Bit (0xC8) Read/Write Initial Value • Bit 7 – LSWRES: Software Reset • Bit 6 – LIN13: LIN 1.3 mode • Bits 5:4 – LCONF[1:0]: Configuration • Bit 3 – LENA: Enable • Bits ...
Page 182
... Bit 4 – LBUSY: Busy Signal • Bit 3 – LERR: Error Interrupt enable bit - LENERR - is set in LINENIR. resets all LINERR bits. • Bit 2 – LIDOK: Identifier Interrupt • Bit 1 – LTXOK: Transmit Performed Interrupt LINENIR. ATtiny87/ATtiny167 182 LIDST2 LIDST1 LIDST0 ...
Page 183
Bit 0 – LRXOK: Receive Performed Interrupt LINENIR. 15.6.3 LINENIR – LIN Enable Interrupt Register Bit (0xCA) Read/Write Initial Value • Bits 7:4 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, they ...
Page 184
... LINBTR – LIN Bit Timing Register Bit (0xCC) Read/Write Initial Value • Bit 7 – LDISR: Disable Bit Timing Re synchronization ATtiny87/ATtiny167 184 – error, – Frame_Time_Out error. This bit is cleared when LERR bit in LINSIR is cleared. – error, – Overrun error. ...
Page 185
Bits 5:0 – LBT[5:0]: LIN Bit Timing 15.6.6 LINBRR – LIN Baud Rate Register Bit (0xCD) (0xCE) Bit Read/Write Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved for future use. For compatibility with future ...
Page 186
... LINSEL – LIN Data Buffer Selection Register Bit (0xD1) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LINSEL is written. ATtiny87/ATtiny167 186 LID5 / LP1 LP0 ...
Page 187
Bit 3 – LAINC: Auto Increment of Data Buffer Index • Bits 2:0 – LINDX[2:0]: FIFO LIN Data Buffer Index The FIFO data buffer is accessed through LINDAT. 15.6.10 LINDAT – LIN Data Register Bit (0xD2) Read/Write Initial Value ...
Page 188
... ATtiny87/167 proposes to have an external resistor used in conjunction with the Current Source. The device measures the voltage to the boundaries of the resistance via the Analog to Digital converter. The resulting voltage defines the physical address that the communication handler will use when the node will participate in LIN communication. ATtiny87/ATtiny167 188 AVCC 100 uA ...
Page 189
The internal Current Source solution of ATtiny87/167 immunizes the address detection against any kind of voltage variations. Table 16-1. Physical Address Table 16-2. Physical Address Note: 8265B–AVR–09/10 Example of Resistor Values(±5%) for a 8-address System (AV Resistor Value Typical Measured ...
Page 190
... Writing this bit to one enables the Current Source as shown in to use DIDR register bit function when ISRCEN is set. It also recommended to turn off the Cur- rent Source as soon as possible ( ex: once the ADC measurement is done). ATtiny87/ATtiny167 190 Table 16-2 (See ”AnaComp - Analog Comparator” on page ...
Page 191
ADC – Analog to Digital Converter 17.1 Features • 10-bit Resolution • 1.0 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 260 µs Conversion Time (Low - High Resolution) • kSPS at ...
Page 192
... Figure 17-1. Analog to Digital Converter Block Schematic ATtiny87/ATtiny167 192 8-Bit Data Bus Analog Misc. ADC Multiplexer (AMISCR) Select (ADMUX) Register A & B (ADCSRA/ADCSRB) Internal 2.56 / 1.1V Reference AVCC AGND / AVCC 4 Bandgap Reference Temperature Sensor ADC10 ADC9 ADC8 Pos. AREF ADC7 Input XREF Mux. ADC6 ADC5 ...
Page 193
Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approx- imation. The minimum value represents AGND and the maximum value represents the voltage on AV The voltage reference for the ADC may be ...
Page 194
... If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA register to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. ATtiny87/ATtiny167 194 ADTS[2:0] ADIF ADATE SOURCE 1 ...
Page 195
Prescaling and Conversion Timing Figure 17-3. ADC Prescaler By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution lower resolution than 10 bits is needed, the ...
Page 196
... Figure 17-5. ADC Timing Diagram, Single Conversion ycle Number DC Clock DSC DIF DCH DCL Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion ycle Number DC Clock igger ource DATE DIF DCH DCL ATtiny87/ATtiny167 196 MUX and REFS Sample & Hold Update One Conversion ...
Page 197
Figure 17-7. ADC Timing Diagram, Free Running Conversion ycle Number DC Clock DSC DIF DCH DCL Conversion Table 17-1. Condition First conversion Normal conversions Auto Triggered conversions 17.6 Changing Channel or Reference Selection The MUX[4:0] and REFS[1:0] bits in the ...
Page 198
... ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). ATtiny87/ATtiny167 198 REF will result in codes close to 0x3FF. V REF , internal 1 ...
Page 199
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a source is used, the sampling time will be negligible source with higher impedance is used, the sampling time ...
Page 200
... Ideal value: 0 LSB Figure 17-10. Gain Error • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. ATtiny87/ATtiny167 200 Output Code Offset Error ...