ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet - Page 17

• Manufacturer Part Number: ATtiny167 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny167 Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.3
6.3.1
6.3.2
6.3.3
7701E–AVR–02/11
EEPROM Data Memory
EEPROM Read/Write Access
Atomic Byte Programming
Split Byte Programming
The Atmel
nized as a separate data space in which single bytes can be read and written. The EEPROM
has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described in the following sections specifying the EEPROM address registers,
the EEPROM data register, and the EEPROM control register. For a detailed description of
serial data downloading to the EEPROM, see
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in
tion, however, lets the user software detect when the next byte can be written. If the user code
contains instructions that write to the EEPROM, some precautions must be taken. In heavily
filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the
device for some period of time to run at a voltage lower than the specified minimum for the
clock frequency used. See
avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
See
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction
is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the
next instruction is executed.
Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the
user must write the address into the EEARL Register and data into EEDR Register. If the
EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the
erase/write operation. Both the erase and write cycle are done in one operation and the total
programming time is given in Table 1. The EEPE bit remains set until the erase and write
operations are completed. While the device is busy with programming, it is not possible to do
any other EEPROM operations.
It is possible to split the erase and write cycle into two different operations. This may be useful
if the system requires short access time for some limited period of time (typically if the power
supply voltage falls). In order to take advantage of this method, the locations to be written are
required to have been erased before the write operation. But because the erase and write
operations are split, it is possible to do the erase operations when the system allows time-crit-
ical operations to be done (typically after power-up).
“Atomic Byte Programming” on page 17
®
ATtiny24/44/84 contains 128/256/512 bytes of EEPROM data memory. It is orga-
Atmel ATtiny24/44/84 [Preliminary]
“Preventing EEPROM Corruption” on page 20
“Serial Downloading” on page
and
“Split Byte Programming” on page 17
Table 6-1 on page
23. A self-timing func-
for details on how to
167.
for
17