ATtiny167 Automotive Atmel Corporation, ATtiny167 Automotive Datasheet - Page 33

• Manufacturer Part Number: ATtiny167 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny167 Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7701E–AVR–02/11
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure
is not interrupted.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
“0011”, giving a division factor of eight at start up. This feature should be used if the selected
clock source has a higher frequency than the maximum frequency of the device at the present
operating conditions. Note that any value can be written to the CLKPS bits regardless of the
CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is
chosen if the selected clock source has a higher frequency than the maximum frequency of
the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse
programmed.
Table 7-10.
CLKPS3
CLKPR to zero.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Atmel ATtiny24/44/84 [Preliminary]
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128
256
16
32
64
1
2
4
8
33