ATtiny20 Atmel Corporation, ATtiny20 Datasheet

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ATtiny20

Manufacturer Part Number
ATtiny20
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny20

Flash (kbytes)
2 Kbytes
Pin Count
14
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
5
Hardware Qtouch Acquisition
Yes
Max I/o Pins
12
Ext Interrupts
12
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATtiny20-CCU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATtiny20-CCUR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATtiny20-MMHR
Manufacturer:
ATMEL
Quantity:
20 000
Part Number:
ATtiny20-SSU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATtiny20-XU
Manufacturer:
Atmel
Quantity:
904
Features
High Performance, Low Power AVR
Advanced RISC Architecture
Non-volatile Program and Data Memories
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage:
Programming Voltage:
Speed Grade
Industrial Temperature Range
Low Power Consumption
– 112 Powerful Instructions – Most Single Clock Cycle Execution
– 16 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 12 MIPS Throughput at 12 MHz
– 2K Bytes of In-System Programmable Flash Program Memory
– 128 Bytes Internal SRAM
– Flash Write/Erase Cycles: 10,000
– Data Retention: 20 Years at 85
– One 8-bit Timer/Counter with Two PWM Channels
– One 16-bit Timer/Counter with Two PWM Channels
– 10-bit Analog to Digital Converter
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Master/Slave SPI Serial Interface
– Slave TWI Serial Interface
– In-System Programmable
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes
– Enhanced Power-on Reset Circuit
– Internal Calibrated Oscillator
– 14-pin SOIC/TSSOP: 12 Programmable I/O Lines
– 15-ball UFBGA: 12 Programmable I/O Lines
– 20-pad VQFN: 12 Programmable I/O Lines
– 1.8 – 5.5V
– 5V
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
– Active Mode:
– Idle Mode:
– Power-down Mode:
• 8 Single-ended Channels
• 200 µA at 1 MHz and 1.8V
• 25 µA at 1 MHz and 1.8V
• < 0.1 µA at 1.8V
o
®
C / 100 Years at 25
8-bit Microcontroller
o
C
8-bit
Microcontroller
with 2K Bytes
In-System
Programmable
Flash
ATtiny20
Summary
Rev. 8235BS–AVR–04/11

Related parts for ATtiny20

ATtiny20 Summary of contents

Page 1

... Active Mode: • 200 µ MHz and 1.8V – Idle Mode: • 25 µ MHz and 1.8V – Power-down Mode: • < 0.1 µA at 1.8V ® 8-bit Microcontroller 100 Years 8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny20 Summary Rev. 8235BS–AVR–04/11 ...

Page 2

... PA6 7 VQFN (PCINT4/ADC4) PA4 1 (PCINT3/ADC3) PA3 2 (PCINT2/AIN1/ADC2) PA2 3 (PCINT1/AIN0/ADC1) PA1 4 (PCINT0/ADC0) PA0 5 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect Pinout ATtiny20 in UFBGA PA5 PA4 PA7 PA3 PA2 PA0 GND 14 GND 13 PA0 (ADC0/PCINT0) 12 PA1 (ADC1/AIN0/PCINT1) 11 PA2 (ADC2/AIN1/PCINT2) ...

Page 3

... RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. The port also serves the functions of various special features of the ATtiny20, as listed on 39. 8235BS–AVR–04/11 Table 20-4 on page 175 ...

Page 4

... Overview ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny20 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. PROGRAMMING The AVR core combines a rich instruction set with 16 general purpose working registers and system registers ...

Page 5

... The device is manufactured using Atmel’s high density non-volatile memory technology. The on- chip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny20 AVR is supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 8235BS–AVR–04/11 ...

Page 6

... Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.5 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. ATtiny20 6 ® ® and QMatrix acquisi- ...

Page 7

... DDRB3 – – – PINB3 PUEA6 PUEA5 PUEA4 PUEA3 PORTA6 PORTA5 PORTA4 PORTA3 DDRA6 DDRA5 DDRA4 DDRA3 PINA6 PINA5 PINA4 PINA3 ATtiny20 Bit 2 Bit 1 Bit BORF EXTRF PORF SM1 SM0 SE Pages 28, – – – – CLKMS1 CLKMS0 CLKPS2 CLKPS1 ...

Page 8

... Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. ATtiny20 8 8235BS–AVR–04/11 ...

Page 9

... PC ← then PC ← then PC ← then PC ← then PC ← Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 ATtiny20 Operation Flags #Clocks Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,N,V,S Z,N,V,S ...

Page 10

... Push Register on Stack POP Rd Pop Register from Stack MCU CONTROL INSTRUCTIONS BREAK Break NOP No Operation SLEEP Sleep WDR Watchdog Reset ATtiny20 10 Description SREG(s) ← 0 I/O(A, b) ← 1 I/O(A, b) ← ← Rr(b) Rd(b) ← ← ← ← ← ← ← ...

Page 11

... R: tape & reel 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard- ous Substances (RoHS). 3. Topside marking for ATtiny20: – 1st Line: T20 – 2nd & 3rd Line: manufacturing data 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa- tion and minimum quantities ...

Page 12

... L is the length of the terminal for soldering to a substrate. 5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny20 ...

Page 13

... PIN 1 4.50 (0.177) 4.30 (0.169) 5.10 (0.201) 1.20 (0.047) MAX 4.90 (0.193) 0.15 (0.006) 0.30 (0.012) 0.05 (0.002) 0.19 (0.007) 0.20 (0.008) 0.09 (0.004) 0º~ 8º 0.75 (0.030) 0.45 (0.018) TITLE 14X (Formerly "14T"), 14-lead (4.4 mm Body) Thin Shrink Small Outline Package (TSSOP) ATtiny20 INDEX MARK 6.50 (0.256) 6.25 (0.246) SEATING PLANE DRAWING NO. 14X 05/16/ REV ...

Page 14

... Package Drawing Contact: packagedrawings@atmel.com R ATtiny20 14 TITLE GPC DRAWING NO. REV. 8235BS–AVR–04/11 ...

Page 15

... Ref (4x) K TITLE 20M2, 20-pad 0.85 mm Body, Lead Pitch 0.45 mm, 1.55 x 1.55 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) ATtiny20 C y SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 0.75 0.80 ...

Page 16

... Errata The revision letters in this section refer to the revision of the corresponding ATtiny20 device. 8.1 Rev. A • Lock bits re-programming • MISO output driver is not disabled by Slave Select (SS) signal 1. Lock bits re-programming Attempt to re-program Lock bits to present, or lower protection level (tampering attempt), causes erroneously one, random line of Flash program memory to get erased. The Lock bits will not get changed, as they should not ...

Page 17

... Table 21-2 on page 180 (section updated and moved) “Analog Input Circuitry” on page 119 page 8 “Watchdog Reset” on page 32 66, and Figure 11-7 on page 68 page 69 page 67, and page 69 page 132 181, and Figure 21-8 on page 184 Table 15-4 on page 124 “Errata” on page 217 ATtiny20 page 69 17 ...

Page 18

... Atmel Corporation. All rights reserved. ® Atmel , logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Limited Atmel Munich GmbH Unit 01-5 & ...

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