ATtiny20 Atmel Corporation, ATtiny20 Datasheet

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ATtiny20

Manufacturer Part Number
ATtiny20
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny20

Flash (kbytes)
2 Kbytes
Pin Count
14
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
5
Hardware Qtouch Acquisition
Yes
Max I/o Pins
12
Ext Interrupts
12
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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Features
High Performance, Low Power AVR
Advanced RISC Architecture
Non-volatile Program and Data Memories
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage:
Programming Voltage:
Speed Grade
Industrial Temperature Range
Low Power Consumption
– 112 Powerful Instructions – Most Single Clock Cycle Execution
– 16 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 12 MIPS Throughput at 12 MHz
– 2K Bytes of In-System Programmable Flash Program Memory
– 128 Bytes Internal SRAM
– Flash Write/Erase Cycles: 10,000
– Data Retention: 20 Years at 85
– One 8-bit Timer/Counter with Two PWM Channels
– One 16-bit Timer/Counter with Two PWM Channels
– 10-bit Analog to Digital Converter
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Master/Slave SPI Serial Interface
– Slave TWI Serial Interface
– In-System Programmable
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes
– Enhanced Power-on Reset Circuit
– Internal Calibrated Oscillator
– 14-pin SOIC/TSSOP: 12 Programmable I/O Lines
– 15-ball UFBGA: 12 Programmable I/O Lines
– 20-pad VQFN: 12 Programmable I/O Lines
– 1.8 – 5.5V
– 5V
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
– Active Mode:
– Idle Mode:
– Power-down Mode:
• 8 Single-ended Channels
• 200 µA at 1 MHz and 1.8V
• 25 µA at 1 MHz and 1.8V
• < 0.1 µA at 1.8V
o
®
C / 100 Years at 25
8-bit Microcontroller
o
C
8-bit
Microcontroller
with 2K Bytes
In-System
Programmable
Flash
ATtiny20
Rev. 8235B–AVR–04/11

Related parts for ATtiny20

ATtiny20 Summary of contents

Page 1

... Active Mode: • 200 µ MHz and 1.8V – Idle Mode: • 25 µ MHz and 1.8V – Power-down Mode: • < 0.1 µA at 1.8V ® 8-bit Microcontroller 100 Years 8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny20 Rev. 8235B–AVR–04/11 ...

Page 2

... PA6 7 VQFN (PCINT4/ADC4) PA4 1 (PCINT3/ADC3) PA3 2 (PCINT2/AIN1/ADC2) PA2 3 (PCINT1/AIN0/ADC1) PA1 4 (PCINT0/ADC0) PA0 5 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect Pinout ATtiny20 in UFBGA PA5 PA4 PA7 PA3 PA2 PA0 GND 14 GND 13 PA0 (ADC0/PCINT0) 12 PA1 (ADC1/AIN0/PCINT1) 11 PA2 (ADC2/AIN1/PCINT2) ...

Page 3

... RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. The port also serves the functions of various special features of the ATtiny20, as listed on 39. 8235B–AVR–04/11 Table 20-4 on page 175 ...

Page 4

... Overview ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny20 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. PROGRAMMING The AVR core combines a rich instruction set with 16 general purpose working registers and system registers ...

Page 5

... The device is manufactured using Atmel’s high density non-volatile memory technology. The on- chip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny20 AVR is supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 8235B–AVR–04/11 ...

Page 6

... Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.5 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. ATtiny20 6 ® ® and QMatrix acquisi- ...

Page 7

... Register File – in one clock cycle. 8235B–AVR–04/11 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATtiny20 Data Bus 8-bit Status Interrupt and Control Unit Watchdog Timer General Purpose Analog Registrers ...

Page 8

... This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny20 8 for a detailed description. “Instruction Set Sum- “ ...

Page 9

... R27 R28 R29 R30 R31 A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny20 implements only 16 registers. For reasons of compatibility the registers are numbered R16:R31 and not R0:R15. ATtiny20 0 X-register Low Byte X-register High Byte Y-register Low Byte ...

Page 10

... The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of SRAM. See 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. ATtiny20 10 The X-, Y-, and Z-registers R27 ...

Page 11

... Har- shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Result Write Back ATtiny20 “Interrupts” on page 38. The list also ...

Page 12

... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny20 12 ; set Global Interrupt Enable ; enter sleep, waiting for interrupt ...

Page 13

... Hence, a stack PUSH command decreases the stack pointer. The stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. In ATtiny20, the SPH register has not been implemented. 8235B–AVR–04/ ...

Page 14

... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See document “AVR Instruction Set” and section • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR Instruction Set” and section ATtiny20 ...

Page 15

... Memories This section describes the different memories in the ATtiny20. The device has two main memory areas, the program memory space and the data memory space. 5.1 In-System Re-programmable Flash Program Memory The ATtiny20 contains 2K byte on-chip, in-system reprogrammable Flash memory for program storage ...

Page 16

... Figure 5-1. 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 5-2. ATtiny20 16 Data Memory Map (Byte Addressing) I/O SPACE SRAM DATA MEMORY (reserved) NVM LOCK BITS (reserved) ...

Page 17

... I/O Memory The I/O space definition of the ATtiny20 is shown in All ATtiny20 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between the 16 general purpose work- ing registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. See document “ ...

Page 18

... The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usu- ally active simultaneously with the CPU clock. ATtiny20 18 presents the principal clock systems and their distribution in ATtiny20. All of the “Power Management and Sleep Modes” on page Clock Distribution ANALOG-TO-DIGITAL ...

Page 19

... Oscillator Speed” on page 205 Table 20-2 on page 174. “Calibration Section” on page External Clock Drive Configuration EXTERNAL CLOCK SIGNAL page 19) for more details. 166. CLKI GND ATtiny20 Table Figure 6-2. 19 ...

Page 20

... The first step after the reset source has been released consists of the device counting the reset start-up time. The purpose of this reset start-up time is to ensure that supply ATtiny20 20 22. When switching between any clock sources, the clock system ensures “ ...

Page 21

... The start-up time is measured in main clock oscillator cycles. 2. When using software BOD disable, the wake-up time from sleep mode will be approximately 60 µs. for details of reset start-up time. Table 6-1 for details of the Total start-up time oscillator cycles + 21 system clock cycles for details. Total start-up time 6 oscillator cycles ATtiny20 (1)(2) (1)(2) 21 ...

Page 22

... These bits are reserved and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written at run-time to vary the clock frequency and suit the application ATtiny20 ...

Page 23

... CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R – CAL[7:0]: Oscillator Calibration Value Table 20-2, “Calibration Accuracy of Internal RC Oscillator,” on page ATtiny20 Table CLKPS0 Clock Division Factor (default 128 0 256 1 Reserved 0 Reserved ...

Page 24

... Oscillator,” on page The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and a setting of 0xFF gives the highest frequency. ATtiny20 24 Table 20-2, “Calibration Accuracy of Internal RC 174. Calibration outside the range given is not guaranteed. ...

Page 25

... Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow. If wake-up from the analog comparator interrupt is not required, the 8235B–AVR–04/11 presents the different clock systems and their distribution in ATtiny20. Active Clock Domains and Wake-up Sources in Different Sleep Modes. Active Clock Domains X 1 ...

Page 26

... Stand-By, while writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active. Writing to the BODS bit is controlled by a timed sequence, see ter” on page ATtiny20 26 109. This will reduce power consumption in idle mode. level has dropped during the sleep period. ...

Page 27

... Timer” on page 33 “Brown-out Detection” on page 32 for details on how to configure the Brown-out Detector. for examples. In all “Analog Comparator” on “Analog to Digital Converter” on page 112 for details on how to configure the Watchdog Timer. and “Software BOD Dis- ATtiny20 29, pro- for 27 ...

Page 28

... These bits select between available sleep modes, as shown in Table 7-2. SM2 ATtiny20 stopped, the input buffers of the device will be disabled. This ensures that I/O for details on which pins are enabled. If the input / input pin can cause significant current even in active mode. Digital ...

Page 29

... Sleep Mode Select (Continued) SM1 SM0 – – – PRTWI R ATtiny20 Sleep Mode Reserved Standby Reserved Reserved Reserved PRSPI PRTIM1 PRTIM0 PRADC R/W R/W R/W R PRR 29 ...

Page 30

... This allows the power to reach a stable level before normal operation starts. The start up sequence is described in 8.2 Reset Sources The ATtiny20 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length • ...

Page 31

... The reset signal is activated again, without any delay, when CC MCU Start-up, RESET Tied POT CC V RST t TOUT MCU Start-up, RESET Extended Externally V POT CC > t TOUT and Figure 8- RST t TOUT “System and Reset Characteristics” on page TOUT ATtiny20 175) – on its RST – has expired. Fig- 31 ...

Page 32

... CC 8.2.4 Brown-out Detection ATtiny20 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...

Page 33

... TIME-OUT INTERNAL 8.3 Internal Voltage Reference ATtiny20 features an internal bandgap reference. This reference is used for Brown-out Detec- tion, and it can be used as an input to the Analog Comparator or the ADC. The bandgap voltage varies with supply voltage and temperature. 8.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...

Page 34

... Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. Write the signature for change enable of protected I/O registers to register CCP 2. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant ATtiny20 34 Watchdog Timer 128 kHz ...

Page 35

... CCP, r16 ; Within four instruction cycles, turn off WDT ldi r16, (0<<WDE) out WDTCSR, r16 ret See “Code Examples” on page WDIF WDIE WDP3 – R/W R/W R ATtiny20 WDE WDP2 WDP1 WDP0 WDTCSR R/W R/W R/W R ...

Page 36

... The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 8-3 on page Table 8-3. WDP3 ATtiny20 36 Watchdog Timer Configuration (1) WDE WDIE Mode 0 0 Stopped 0 1 Interrupt 1 0 ...

Page 37

... Watchdog Timer Prescale Select (Continued) WDP2 WDP1 WDP0 WDT Oscillator Cycles – – – – ATtiny20 Number of Typical Time-out Reserved WDRF BORF EXTRF PORF RSTFLR R/W R/W R/W R 5.0V 37 ...

Page 38

... Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny20. For a general explanation of the AVR interrupt handling, see 11. 9.1 Interrupt Vectors The interrupt vectors of ATtiny20 are described in Table 9-1. Vector No case the program never enables an interrupt source, the Interrupt Vectors will not be used and, consequently, regular program code can be placed at these locations ...

Page 39

... A typical and general setup for interrupt vector addresses in ATtiny20 is shown in the program example below. Assembly Code Example .org 0x0000 RESET: Note: 9.2 External Interrupts External Interrupts are triggered by the INT0 pin or any of the PCINT[11:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT[11:0] pins are configured as out- puts ...

Page 40

... SLEEP command. 9.2.2 Pin Change Interrupt Timing A timing example of a pin change interrupt is shown in Figure 9-1. PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF ATtiny20 40 Timing of pin change interrupts pin_lat D Q pin_sync LE clk PCINT(0) in PCMSK(x) clk “Clock System” on page Figure 9-1 ...

Page 41

... Any logical change on INT0 generates an interrupt request. 0 The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request – – PCIE1 PCIE0 R R R/W R ATtiny20 SM1 SM0 SE MCUCR R/W R/W R – ...

Page 42

... If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor- responding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. ATtiny20 ...

Page 43

... I/O pin is disabled. 8235B–AVR–04/ – – – – PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATtiny20 PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK1 ...

Page 44

... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATtiny20 44 and Ground as indicated in Figure 10-1 on page for a complete list of parameters. ...

Page 45

... PORTxn Q CLR RESET WRx RRx RPx PINxn Q Q clk I/O WEx: WRITE PUEx REx: READ PUEx WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER ATtiny20 shows a func- WPx 45 ...

Page 46

... The Break-Before-Make mode applies to the entire port and it is activated by the BBMx bit. For more details, see When switching the DDRxn bit from output to input no immediate tri-state period is introduced. ATtiny20 46 summarizes the control signals for the pin value. Port Pin Configurations ...

Page 47

... Figure 10-2 on page XXX PINxn r17 0x02 0x01 nop out DDRx, r17 0x55 0x01 tri-state intermediate tri-state cycle 45, the PINxn Register bit and the preced- and t pd,max pd,min XXX in r17, PINx 0x00 t pd, max t pd, min ATtiny20 Figure 10-4 respectively. 0xFF 47 ...

Page 48

... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pulldown. Connecting unused pins directly to V accidentally configured as an output. ATtiny20 48 Figure 10-5 on page 48. The out instruction sets the “SYNC LATCH” signal at the ...

Page 49

... Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PUEB2) ldi r17,(1<<PB0) ldi r18,(1<<DDB1)|(1<<DDB0) out PUEB,r16 out PORTB,r17 out DDRB,r18 ; Insert nop for synchronization nop ; Read port pins in r16,PINB ... See “Code Examples” on page 6. ATtiny20 Figure 10-6 Figure 10-2 on page 45 can 49 ...

Page 50

... DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn: Note: The illustration in the figure above serves as a generic description applicable to all port pins in the AVR microcontroller family. Some overriding signals may not be present in all port pins. ATtiny20 50 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 ...

Page 51

... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/Output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATtiny20 51 ...

Page 52

... Analog Comparator. • PCINT1: Pin Change Interrupt source 1. The PA1 pin can serve as an external interrupt source for pin change interrupt 0. ATtiny20 52 Port A Pins Alternate Functions Port Pin ...

Page 53

... SPI is enabled as a slave. The data direction of the pin is controlled by DDA7 when SPI is enabled as a master. • PCINT7: Pin Change Interrupt source 7. The PA7 pin can serve as an external interrupt source for pin change interrupt 0. 8235B–AVR–04/11 ATtiny20 . . . . ...

Page 54

... Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny20 54 and Table 10-5 relate the alternate functions of Port A to the overriding signals Figure 10-6 on page 50. Overriding Signals for Alternate Functions in PA[7:5] PA7/ADC7/OC0B/ICP1/ T1/SCL/SCK/PCINT7 PA6/ADC6/SS/PCINT6 0 0 TWEN + (SPE • MSTR) TWEN • ...

Page 55

... OC0A: Timer/Counter0 Compare Match A output OC1B: Timer/Counter1 Compare Match B output PB2 MISO: SPI Master Input / Slave Output CKOUT: System Clock Output PCINT10:Pin Change Interrupt 1, Source 10 RESET: Reset pin PB3 PCINT11:Pin Change Interrupt 1, Source 11. ATtiny20 PA0/ADC0/PCINT0 PCINT0 • PCIE0 + ADC0D PCINT0 • ...

Page 56

... RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. • PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external interrupt source for pin change interrupt 1. ATtiny20 56 “External Clock” on page 19. ...

Page 57

... EXT_CLOCK = external clock is selected as system clock. When TWI is enabled the slew rate control and spike filter are activate on PB1. This is not illus- trated in Figure 10-6 on page 50. The spike filter is connected between AIOxn and the TWI. ATtiny20 relate the alternate functions of Port B to the 50. PB2/INT0/OC0A/OC1B/MISO/CKOUT/PCINT10 (2) ...

Page 58

... DDRA – Port A Data Direction Register Bit 0x01 Read/Write Initial Value 10.4.5 PINA – Port A Input Pins Bit 0x00 Read/Write Initial Value 10.4.6 PUEB – Port B Pull-up Enable Control Register Bit 0x07 Read/Write Initial Value ATtiny20 – – – – “ ...

Page 59

... – – – – – – – – ATtiny20 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R PINB3 ...

Page 60

... A simplified block diagram of the 8-bit Timer/Counter is shown in the actual placement of I/O pins, refer to including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the Figure 11-1. 8-bit Timer/Counter Block Diagram ATtiny20 60 Figure 1-1 on page “Register Description” on page Count ...

Page 61

... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment depends on the mode of operation “Timer/Counter Prescaler” on page shows a block diagram of the counter and its surroundings. ATtiny20 Figure 11-1) signals are all visible in the for details. The Compare Match event will also 105 ...

Page 62

... The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM0[2:0] bits and Compare Output mode (COM0x[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation. See ATtiny20 62 DATA BUS count ...

Page 63

... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 8235B–AVR–04/11 shows a block diagram of the Output Compare unit. DATA BUS OCRnx 8-BIT COMPARATOR top bottom WAVEFORM GENERATOR FOCn WGMn[2:0] ATtiny20 TCNTn OCFnx (Int.Req.) OCnx COMnX[1:0] 63 ...

Page 64

... The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction ATtiny20 64 Waveform ...

Page 65

... Description” on page 71 Table 11-2 on page 72, and for phase correct PWM refer to “TCCR0B – Timer/Counter Control Register B” on page “Modes of Operation” on page Figure 11-8 on page and Figure 11-11 on page 71 ATtiny20 71. For fast PWM mode, refer to Table 11-4 on page 72. 65). 70, Figure 11-9 on page in “Timer/Counter Timing Diagrams” on page 74 ...

Page 66

... TOM. TOP is defined as 0xFF when WGM0[2: and OCR0A when WGM0[2: non- inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the out- put is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the ATtiny20 66 Figure 11-5 on page 1 ...

Page 67

... Figure 11-6 on page 67. The TCNT0 value is in the timing diagram Table 11-3 on page f = ---------------------------------- - OCnxPWM N ATtiny20 OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx[1: (COMnx[1: 72). The actual OC0x value will only be vis- f clk_I/O ⋅ ...

Page 68

... TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The ATtiny20 11-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating /2 when OCR0A is set to zero ...

Page 69

... PWM mode. 8235B–AVR–04/11 Table 11-4 on page f = OCnxPCPWM Figure 11-7 on page 68 Figure 11-7 on page Figure 11-8 on page 70 contains timing data for basic Timer/Counter operation. ATtiny20 72). The actual OC0x value will only be f clk_I/O ------------------------------- - × × TOP OCnx has a transition from high to low 68 ...

Page 70

... Tn (clk /8) I/O TCNTn OCRnx OCFnx Figure 11-11 on page 71 and fast PWM mode where OCR0A is TOP. ATtiny20 70 MAX - 1 MAX shows the same timing data, but with the prescaler enabled. MAX - 1 MAX shows the setting of OCF0B in all modes and OCF0A in all modes OCRnx - 1 OCRnx ...

Page 71

... Compare Output Mode, non-PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. 1 Toggle OC0A on Compare Match 0 Clear OC0A on Compare Match 1 Set OC0A on Compare Match shows COM0A[1:0] bit functionality when WGM0[2:0] bits are set to fast PWM mode. ATtiny20 BOTTOM TOP – – WGM01 WGM00 R ...

Page 72

... When OC0B is connected to the pin, the function of COM0B[1:0] bits depend on WGM0[2:0] bit setting. or CTC mode (non-PWM). Table 11-5. COM0B1 ATtiny20 72 Compare Output Mode, Fast PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected WGM02 = 0: Normal Port Operation, OC0A Disconnected 1 WGM02 = 1: Toggle OC0A on Compare Match ...

Page 73

... A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See page 68 for more details. Table 11-8. Modes of operation supported by the Timer/Counter (1) “Fast PWM Mode” on (1) “Phase Correct PWM Mode” on “Modes of Operation” on page 65). ATtiny20 73 ...

Page 74

... Compare Match is forced on the Waveform Generation unit. The OC0B output is changed according to its COM0B[1:0] bits setting. Note that the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B[1:0] bits that determines the effect of the forced compare. ATtiny20 74 Waveform Generation Mode Bit Description WGM02 ...

Page 75

... OCR0B as TOP. The FOC0B bit always reads as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny20 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS0[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...

Page 76

... Bit 2 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor- responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to ATtiny20 ...

Page 77

... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM0[2:0] bit setting. See and “Waveform Generation Mode Bit Description” on page 8235B–AVR–04/11 ATtiny20 Table 11-8 on page 74 74. 77 ...

Page 78

... I/O pins, refer to ters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in section Figure 12-1. 16-bit Timer/Counter Block Diagram ATtiny20 78 “Pinout of ATtiny20” on page “Register Description” on page Count Clear Control Logic Direction clk ...

Page 79

... The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX), the value 1 stored in the OCR A register, or the value stored in the ICR1 register. The assignment depends on the mode of operation ATtiny20 “Accessing 16-bit Registers” on page ). T1 “Out- 79 ...

Page 80

... Clock Select bits (CS1[2:0]). When no clock source is selected (CS1[2: the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clk count operations. ATtiny20 80 “Timer/Counter Prescaler” on page shows a block diagram of the counter and its surroundings. DATA BUS ...

Page 81

... Input Capture Flag generates an Input Capture interrupt. The ICF1 flag is automatically 8235B–AVR–04/11 “Modes of Operation” on page DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) ACO* ACIC* Analog Comparator ATtiny20 86. Figure 12-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNCn ICES1 Noise Edge ...

Page 82

... In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter- rupt handler routine as possible. Even though the Input Capture interrupt has relatively high ATtiny20 82 95. ...

Page 83

... DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) TOP Waveform Generator BOTTOM WGMn[3:0] ATtiny20 86). TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCFnx (Int.Req.) OCnx COMnx[1:0] 83 ...

Page 84

... The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Com- ATtiny20 84 shows a block diagram of the Output Compare unit. The small “n” in the 95. “ ...

Page 85

... The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. See Table 12-4 on page 100 8235B–AVR–04/11 Waveform D Q Generator OCnx D Q PORT D Q DDR Table 12-2 on page for details. ATtiny20 Figure 12-5 shows a 1 OCnx Pin 0 99, Table 12-3 on page 99 and 85 ...

Page 86

... Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM1[3: 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when ATtiny20 86 “Register Description” on page 99 Table 12-2 on page 99, and for phase correct and phase and frequency correct PWM refer to 100. (“ ...

Page 87

... MAX to 0x0000. 8235B–AVR–04/ when OCR1A is set to zero (0x0000). The waveform frequency is defined by clk_I --------------------------------------------------- ⋅ OCnA 2 N ATtiny20 Figure 12-6 on page 87. The counter value OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA[1: clk_I/O ⋅ ...

Page 88

... OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ATtiny20 FPWM 88. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. ...

Page 89

... OC1A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 8235B–AVR–04/11 Table 12-3 on page f clk_I ---------------------------------- - ⋅ OCnxPWM TOP /2 when OCR1A is set to zero (0x0000). This clk_I/O ATtiny20 99). The 89 ...

Page 90

... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x inter- rupt flag will be set when a compare match occurs. Figure 12-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period ATtiny20 log TOP + 1 ...

Page 91

... Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre- 8235B–AVR–04/11 Figure 12-8 f clk_I --------------------------- - ⋅ ⋅ OCnxPCPWM 2 N TOP ATtiny20 illustrates, changing the Table 12-4 on page 91 ...

Page 92

... Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. ATtiny20 92 and Figure 12-9 on page 92) ...

Page 93

... The actual OC1x value will only be visible on the port pin if the data direction f OCnxPFCPWM Figure 12-10 shows a timing diagram for the setting of OCF1x. ATtiny20 f clk_I/O = --------------------------- - ⋅ ⋅ ...

Page 94

... OCRnx OCFnx Figure 12-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. ATtiny20 94 I/O Tn /1) I/O ...

Page 95

... CPU, the high byte of the 16-bit register is copied into the tempo- rary register in the same clock cycle as the low byte is read. 8235B–AVR–04/11 OCRnx - 1 OCRnx OCRnx Value shows the same timing data, but with the prescaler enabled. OCRnx - 1 OCRnx OCRnx Value ATtiny20 OCRnx + 1 OCRnx + 2 /8) clk_I/O OCRnx + 1 OCRnx + 2 95 ...

Page 96

... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ATtiny20 96 See “Code Examples” on page 6. 8235B– ...

Page 97

... Restore global interrupt flag out SREG,r18 ret unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; See “Code Examples” on page 6. ATtiny20 97 ...

Page 98

... If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATtiny20 98 See “ ...

Page 99

... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. See Mode” on page 88 for more details COM1B0 – – WGM11 R R ATtiny20 0 WGM10 TCCR1A R/W 0 “Fast PWM 99 ...

Page 100

... ATtiny20 100 shows COM1x[1:0] bit functionality when WGM1[3:0] bits are set to phase correct or Compare Output Mode, Phase Correct and Phase & Frequency Correct PWM COM1A0 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected WGM13=0: Normal port operation, OC1A/OC1B disconnected ...

Page 101

... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge. ATtiny20 WGM12 CS12 CS11 CS10 R/W R/W R/W R TCCR1B ...

Page 102

... Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com- pare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. ATtiny20 102 ...

Page 103

... OCIE1A R OCR1A[15:8] OCR1A[7:0] R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R ICR1[15:8] ICR1[7:0] R/W R TOIE1 OCIE0B OCIE0A R/W R/W R/W R ATtiny20 0 OCR1AH OCR1AL R OCR1BH OCR1BL R ICR1H ICR1L R TOIE0 TIMSK R/W 0 103 ...

Page 104

... TOV1 flag is set when the timer overflows. See behavior when using another WGM1[3:0] bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATtiny20 104 “Interrupts” on page 38) is executed when the OCF1B flag, located in TIFR, “ ...

Page 105

... Tn pin to the counter is updated. 8235B–AVR–04/11 ). Alternatively, one of four taps from the prescaler can be used CLK_I/O /1024. CLK_I/O pulse for each positive (CSn[2: negative Synchronization ATtiny20 /8, f /64, CLK_I/O CLK_I/O ). The Tn Figure 13-1 shows a functional ). The latch is transparent in the clk I/O Tn_sync D Q ...

Page 106

... An external clock source can not be prescaled. Figure 13-2. Prescaler for Timer/Counter0 clk I/O PSR T0 Note: ATtiny20 106 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O Clear Synchronization 1. The synchronization logic on the input pins ( ...

Page 107

... When this bit is one, the Timer/Counter prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. 8235B–AVR–04/ TSM – – – R ATtiny20 – – – PSR GTCCR R 107 ...

Page 108

... See Figure 1-1 on page 2 The ADC Power Reduction bit, PRADC, must be disabled in order to use the ADC input multi- plexer. This is done by clearing the PRADC bit in the Power Reduction Register, PRR. See “PRR – Power Reduction Register” on page 29 ATtiny20 108 14-1. ACBG HSEL ...

Page 109

... Analog Comparator Negative Input XXXX AIN1 0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 ACD ACBG ACO ACI R/W R N/A 0 ATtiny20 ACIE ACIC ACIS1 ACIS0 R/W R/W R/W R ACSRA 109 ...

Page 110

... ACSRB – Analog Comparator Control and Status Register B Bit 0x13 Read/Write Initial Value • Bit 7 – HSEL: Hysteresis Select When this bit is written logic one, the hysteresis of the analog comparator is enabled. The level of hysteresis is selected by the HLEV bit. ATtiny20 110 Table 14-2. ACIS1/ACIS0 Settings ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle ...

Page 111

... Selecting Level of Analog Comparator Hysteresis HLEV Hysteresis of Analog Comparator 0 X Not enabled “Analog Comparator Multiplexed Input” on page ADC7D ADC6D ADC5D R/W R/W R 109 ADC4D ADC3D ADC2D ADC1D R/W R/W R/W R ATtiny20 0 ADC0D DIDR0 R/W 0 111 ...

Page 112

... Sleep Mode Noise Canceler 15.2 Overview ATtiny20 features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). The ADC is wired to a nine-channel analog multiplexer, which allows the ADC to measure the volt- age at eight single-ended input pins, or from one internal, single-ended voltage channel coming from the internal temperature sensor. Voltage inputs are referred to 0V (GND). ...

Page 113

... SELECT SELECT INTERNAL INTERNAL REFERENCE REFERENCE TEMPERATURE TEMPERATURE SENSOR SENSOR INPUT INPUT MUX MUX AGND for more details. ATtiny20 ADCH+ADCL ADCH+ADCL ADCSRA ADCSRA ADC IRQ ADC IRQ PRESCALER PRESCALER CONVERSION LOGIC CONVERSION LOGIC 10-BIT DAC 10-BIT DAC - + SAMPLE & HOLD SAMPLE & HOLD ...

Page 114

... Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. ATtiny20 114 supply pin and the internal 1.1V voltage reference. CC “ ...

Page 115

... ADC clock frequency from any CPU frequency above 100 kHz. The 8235B–AVR–04/11 ADTS[2:0] ADIF SOURCE EDGE DETECTOR SOURCE n ADSC ADEN Reset START CK ADPS0 ADPS1 ADPS2 PRESCALER START ADATE CONVERSION LOGIC 7-BIT ADC PRESCALER ADC CLOCK SOURCE Figure 15-3 on page 115, which gener- ATtiny20 CLK ADC 115 ...

Page 116

... ADC clock edge. Figure 15-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 15-6 ATtiny20 116 First Conversion ...

Page 117

... ADCL Conversion Complete One Conversion Conversion Complete 15-7. Next Conversion Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update ATtiny20 Next Conversion 1 2 Sign and MSB of Result LSB of Result Prescaler Reset 117 ...

Page 118

... In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the ATtiny20 118 Table 15-1 ...

Page 119

... S/H capacitor. 8235B–AVR–04/11 ) indicates the conversion range for the ADC. Single ended REF will result in codes close to 0x3FF. V REF ) through an internal amplifier. BG ATtiny20 can be selected as either REF Figure 15-8. An analog 119 ...

Page 120

... An n-bit single-ended ADC converts a voltage linearly between GND and V (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior, as follows: ATtiny20 120 /2) should not be present. The user is advised to remove high fre- ...

Page 121

... Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 15-10. Gain Error Output Code 8235B–AVR–04/11 Offset Error ATtiny20 Ideal ADC Actual ADC V Input Voltage REF Gain Error ...

Page 122

... Figure 15-11. Integral Non-linearity (INL) Output Code • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 15-12. Differential Non-linearity (DNL) ATtiny20 122 Output Code 0xFF 1 LSB ...

Page 123

... LSB Table 15-2 are typical values. However, due to process variation the ⋅ 1024 -------------------------- V REF the selected voltage reference (see REF 124). 0x000 represents analog ground, and +25°C 300 LSB OS ATtiny20 Table 15-2 °C, 10 +85°C 370 LSB is the OS 123 ...

Page 124

... The value of these bits selects which analog input is connected to the ADC, as shown in 15-4. Selecting channel ADC8 enables temperature measurement. Table 15-4. Single Ended Input ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC4 (PA4) ADC5 (PA5) ADC6 (PA6) ADC7 (PA7) 0V (AGND) ATtiny20 124 – REFS REFEN ADC0EN R R/W R/W 0 ...

Page 125

... ADC6 ADC5 ADC4 ADC3 – – – – “ADC Conversion Result” on ATtiny20 8 ADC8 ADCH ADC0 ADCL ADC2 ADCH – ADCL 125 ...

Page 126

... ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter- rupt is activated. ATtiny20 126 ...

Page 127

... VDEN VDPD – R/W R ADPS0 Division Factor 128 – ADLAR ADTS2 ADTS1 R R/W R/W R “ADCL and ADCH – ADC Data Register” on ATtiny20 0 ADTS0 ADCSRB R/W 0 127 ...

Page 128

... The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[7:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATtiny20 128 ADC Auto Trigger Source Selections ...

Page 129

... Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 16.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATtiny20 and peripheral devices or between several AVR devices. The SPI module is illustrated in Figure Figure 16-1. SPI Block Diagram Note: 8235B–AVR–04/11 16-1 ...

Page 130

... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: ATtiny20 130 “PRR – Power Reduction Register” on page 29 ...

Page 131

... SPCR,r17 ret ; Start transmission of data (r16) out SPDR,r16 ; Wait for transmission complete in r16, SPSR sbrsr16, SPIF rjmp Wait_Transmit ret ATtiny20 Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 131 ...

Page 132

... Enable SPI ldi out ret SPI_SlaveReceive: ; Wait for reception complete in sbrs r16, SPIF rjmp SPI_SlaveReceive ; Read received data and return in ret ATtiny20 132 ; See ”Code Examples” on page 6. r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16, SPSR r16,SPDR 8235B–AVR–04/11 ...

Page 133

... To avoid bus contention, the SPI system takes the following actions: 8235B–AVR–04/11 /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; See ”Code Examples” on page 6. ATtiny20 133 ...

Page 134

... Figure 16-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) ATtiny20 134 and Figure 16-4 on page 135. MSB Bit 6 Bit 5 Bit 4 LSB Bit 1 Bit 2 Bit 3 Figure ...

Page 135

... Table 16-2, which is a summary of Leading Edge Trailing eDge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) Setup (Rising) Setup (Falling) Sample (Rising MSTR CPOL CPHA SPR1 R/W R/W R/W R ATtiny20 Bit 1 LSB Bit 6 MSB Table 16-3 0 SPR0 SPCR R/W 0 135 ...

Page 136

... Bits 1:0 – SPR[1:0]: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the I/O clock frequency f shown in the following table: Table 16-5. SPI2X ATtiny20 136 Figure 16-3 and Figure 16-4 CPOL Functionality ...

Page 137

... SPIF WCOL – – R/W R Table 16-5). This means that the minimum SCK period will be two I MSB R/W R/W R/W R ATtiny20 – – – SPI2X R LSB R/W R/W R/W R SPSR SPDR ...

Page 138

... One bus can have several masters, and an arbitration process handles priority if two or more masters try to transmit at the same time. The TWI module in ATtiny20 implements slave functionality, only. Lost arbitration, errors, colli- sions and clock holds on the bus are detected in hardware and indicated in separate status flags ...

Page 139

... After all data packets (DATA) are transferred, the mas- ter issues a STOP condition (P) on the bus to end the transaction. The receiver must acknowledge (A) or not-acknowledge (A) each byte received. Figure 17-2 Figure 17-2. Basic TWI Transaction Diagram Topology 8235B–AVR–04/11 illustrates the TWI bus topology. shows a TWI transaction. ATtiny20 139 ...

Page 140

... The addressed device signals ACK by pulling the SCL line low, and NACK by leaving the line SCL high during the ninth clock cycle. ATtiny20 140 144. ...

Page 141

... The addressed slave must acknowledge the address for the master to be allowed to continue the transaction. 8235B–AVR–04/11 illustrates the Master Write transaction. The master initiates the transaction by issu- illustrates the Master Read transaction. The master initiates the transaction by issu- ATtiny20 141 ...

Page 142

... Both the master and slave device can randomly stretch the clock on a byte level basis before and after the ACK/NACK bit. This pro- vides time to process incoming or prepare outgoing data, or performing other time critical tasks. ATtiny20 142 illustrates a combined transaction. A combined transaction consists of several read Figure 17-8 ...

Page 143

... The SCL line is the wired-AND result of the two masters clock outputs. 8235B–AVR–04/11 shows an example where two TWI masters are contending for bus ownership. Both ATtiny20 Figure 17-10 shows an example where 143 ...

Page 144

... TWI Slave Operation The TWI slave is byte-oriented with optional interrupts after each byte. There are separate inter- rupt flags for Data Interrupt and Address/Stop Interrupt. Interrupt flags can be set to trigger the ATtiny20 144 2 C-compliant interface there are known compatibility issues the designer Figure 10-1 on page 146 ...

Page 145

... If ACK is sent by the slave, the slave hardware will set the Data Interrupt Flag indicating data is needed for transmit. If NACK is sent by the slave, the slave will wait for a new START condition and address match. 8235B–AVR–04/11 ATtiny20 Figure 17-11. shows the 145 ...

Page 146

... Bit 6 – Res: Reserved Bit This bit is reserved and will always read as zero. • Bit 5 – TWDIE: TWI Data Interrupt Enable When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the data interrupt flag (TWDIF) in TWSSRA is set. ATtiny20 146 ...

Page 147

... Send NACK – – TWAA TWCMD1 TWCMD0 Table 17-1 for details. When When TWCMDn bits are written When TWSD is read When TWCMDn bits are written When TWSD is read ATtiny20 0 TWSCRB W 0 147 ...

Page 148

... This flag is set when the slave detects that a valid address has been received, or when a trans- mit collision has been detected. When this flag is set the slave forces the SCL line low, stretching the TWI clock period. The SCL line is released by clearing the interrupt flags. ATtiny20 148 TWI Slave Command ...

Page 149

... No low values are shifted out onto the SDA line. This bit is cleared by writing a one to it. The bit is also cleared automatically when a START or Repeated START condition is detected. 8235B–AVR–04/11 ATtiny20 149 ...

Page 150

... The data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware. The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set. ATtiny20 150 7 6 ...

Page 151

... By default, this bit is zero and the TWSAM bits acts as an address mask to the TWSA register. If this bit is set to one, the slave address match logic responds to the two unique addresses in TWSA and TWSAM. 8235B–AVR–04/ TWSAM[7:1] R/W R/W R/W R ATtiny20 TWAE R/W R/W R/W R TWSAM 151 ...

Page 152

... The physical layer includes serial-to-parallel and parallel-to-serial data conversion, start-of-frame detection, frame error detection, parity error detection, parity generation and collision detection. ATtiny20 152 “Memory Programming” on page TINY PROGRAMMING INTERFACE (TPI) ...

Page 153

... RESET pin. The RESET pin must be kept at 12V for the entire programming session (see Table 20-4 on page 175) RST for guidance. t RST “TPISR – Tiny Programming Interface Status Register” on page ATtiny20 175) and then set the RESET pin low TPICLK CYCLES is no longer applied to the HV 162. 153 ...

Page 154

... Figure 18-4. Supported characters. TPIDATA TPIDATA TPIDATA 18.3.6 Operation The TPI physical layer operates synchronously on the TPICLK provided by the external pro- grammer. The dependency between the clock edges and data sampling or data change is shown in ATtiny20 154 IDLE Figure 18-3: Start bit (always low) ...

Page 155

... A possible drive contention may occur, if the external programmer and the TPI physical layer drive the TPIDATA line simultaneously. In order to reduce the effect of the drive contention, a collision detection mechanism is supported. The collision detection is based on the way the TPI physical layer drives the TPIDATA line. 8235B–AVR–04/11 TPICLK TPIDATA SAMPLE SETUP ATtiny20 155 ...

Page 156

... The Control and Status Space (CSS) of the Tiny Programming Interface is allocated for control and status registers in the TPI access Layer. The CSS consist of registers directly involved in the operation of the TPI itself. These register are accessible using the SLDCS and SSTCS instructions. ATtiny20 156 8235B–AVR–04/11 ...

Page 157

... The instructions allow the external programmer to access the TPI, the NVM Controller and the NVM memories. All instructions except SKEY require one byte oper- and following the instruction. The SKEY instruction is followed by 8 data bytes. All instructions are byte-sized. 8235B–AVR–04/11 page 157. ATtiny20 157 ...

Page 158

... The data space location is pointed by the Pointer Register (PR), where the address must have been stored before the operation. The Pointer Register can be either left unchanged by the operation can be post-incremented, as shown in Table 18-3. Operation DS[PR] DS[PR] ATtiny20 158 Table Instruction Set Summary Operand Description Serial LoaD from data space using indirect ...

Page 159

... Bits marked ‘a’ form the direct, 6-bit addres Remarks Bits marked ‘a’ form the direct, 6-bit addres Remarks Bits marked ‘a’ form the direct, 4-bit addres Remarks Bits marked ‘a’ form the direct, 4-bit addres ATtiny20 Table 18-7. Table 18-8. 159 ...

Page 160

... Table 18-11. Summary of Control and Status Registers Addr. 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 ATtiny20 160 The Serial KEY signaling (SKEY) Instruction Opcode 1110 0000 {8[data}} Table Name Bit 7 Bit 6 Bit 5 TPIIR Tiny Programming Interface Identification Code Reserved – ...

Page 161

... Value 0x80 – GT2 GT1 GT0 R R/W R/W R GT0 Guard Time (Number of IDLE bits) 0 +128 (default value) 1 +64 0 + ATtiny20 Bit 1 Bit 0 GT1 GT0 – – NVMEN – TPIIR TPIPCR 161 ...

Page 162

... These bits are reserved and will always read as zero. • Bit 1 – NVMEN: Non-Volatile Memory Programming Enabled NVM programming is enabled when this bit is set. The external programmer can poll this bit to verify the interface has been successfully enabled. NVM programming is disabled by writing this bit to zero. ATtiny20 162 GT1 GT0 1 ...

Page 163

... The external programmer can read and program the NVM via the Tiny Programming Interface (TPI). In the external programming mode all NVM can be read and programmed, except the signature and the calibration sections which are read-only. NVM can be programmed at 5V, only. See 8235B–AVR–04/11 Table 20-9 on page 178. ATtiny20 163 ...

Page 164

... The ATtiny20 has the following, embedded NVM: • Non-Volatile Memory Lock Bits • Flash memory with four separate sections 19.3.1 Non-Volatile Memory Lock Bits The ATtiny20 provides two Lock Bits, as shown in Table 19-1. Lock Bit NVLB2 NVLB1 The Lock Bits can be left unprogrammed ("1") or can be programmed ("0") to obtain the addi- tional security shown in command, only ...

Page 165

... Flash Memory The embedded Flash memory of ATtiny20 has four separate sections, as shown in Table 19-3. Section Code (program memory) Configuration Signature Calibration Notes: 19.3.3 Configuration Section ATtiny20 has one configuration byte, which resides in the configuration section. See Table 19-4. Configuration word address 0x00 0x01 ... 0x0F Table 19-5 into the configuration byte ...

Page 166

... Most of this memory section is reserved for internal use, as shown in Table 19-6. Signature word address 0x00 0x01 0x02 ... 0x1F ATtiny20 has a three-byte signature code, which can be used to identify the device. The three bytes reside in the signature section, as shown in given in Table 19-7. Part ATtiny20 19.3.5 Calibration Section ATtiny20 has one calibration byte ...

Page 167

... Programming any part of the NVM will automatically inhibit the following operations: • All programming to any other part of the NVM • All reading from any NVM location The ATtiny20 supports only external programming. Internal programming operations to the NVM have been disabled, which means any internal attempt to write or erase NVM locations will fail. 19.4.1 ...

Page 168

... The Chip Erase can be carried out as follows: 1. Write the CHIP_ERASE command to the NVMCMD register 2. Start the erase operation by writing a dummy byte to the high byte of any word location inside the code section 3. Wait until the NVMBSY bit has been cleared ATtiny20 168 8235B–AVR–04/11 ...

Page 169

... Flash write operation 7. Wait until the NVMBSY bit has been cleared 19.4.4 Reading NVM Lock Bits The Non-Volatile Memory Lock Byte can be read from the mapped location in data memory. 8235B–AVR–04/11 ATtiny20 “Supported Characters” on page 154 “Supported Characters” on page 154 169 ...

Page 170

... NVM Lock Word location. 4. Wait until the NVMBSY bit has been cleared. 19.5 Self programming The ATtiny20 doesn't support internal programming. 19.6 External Programming The method for programming the Non-Volatile Memories by means of an external programmer is referred to as external programming. External programming can be done both in-system or in mass production ...

Page 171

... NVMBSY – – – R ATtiny20 Table 19-9. Mnemonic Description NO_OPERATION No operation CHIP_ERASE Chip erase SECTION_ERASE Section erase DWORD_WRITE Write double word – – – – NVMCSR ...

Page 172

... Input Leakage I LIL Current I/O Pin Input Leakage I LIH Current I/O Pin R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor PU Analog Comparator I ACLK Input Leakage Current ATtiny20 172 ° ° *NOTICE +125 C ° ° +150 C +0. -40°C to +85°C A Condition Min V = 1. ...

Page 173

... Idle 4 MHz Idle 8 MHz WDT enabled WDT disabled (for all ports) should not exceed 100 mA (for all ports) should not exceed 100 mA Figure 21-30 on page “Minimizing Power Consumption” on page ATtiny20 (1) Typ Max 0.2 0.6 1.1 2 3.2 5 0.03 0.2 0.2 0.5 0.8 1.5 4.5 10 ...

Page 174

... Table 20-2. Calibration Accuracy of Internal RC Oscillator Calibration Method Target Frequency Factory 8.0 MHz Calibration User Fixed frequency within: Calibration 7.3 – 8.1 MHz Notes: ATtiny20 174 Figure 20-1, the Maximum Frequency vs MHz 4 MHz 1.8V 2. Fixed voltage within: 1.8V – 5.5V 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). ...

Page 175

... Values are guidelines, only V = 2 4 Max. Min. Max. Min 125 2.0 1.6 2.0 1 (1) (1) Min Typ 0 2.7V CC 1.0 1.1 = 25° 1.8V 2000 700 400 CC 64 128 ATtiny20 Max. Units 12 MHz μs 0.5 μs 0 (1) Max Units 0. 1 128 ms 256 175 ...

Page 176

... APD Analog Propagation Delay (large step change) t Digital Propagation Delay DPD ATtiny20 176 Characteristics of Enhanced Power-On Reset. Parameter Release threshold of power-on reset Activation threshold of power-on reset Power-On Slope Rate 1. Values are guidelines, only 2. Threshold where device is released from reset when voltage is rising 3 ...

Page 177

... IVCH CHIX t t CLC H CHCL t CLCL Min Typ Max 1.5 2.5 1 0.5 2.5 1.5 13 260 50 1000 GND V REF 38.5 100 0 1023 Rec eive Mode Transmit Mode ATtiny20 Units Bits LSB LSB LSB LSB LSB LSB LSB LSB µs kHz V kHz MΩ LSB t CLO V 177 ...

Page 178

... CLCL t CLCH t CHCH t IVCH t CHIX t CLOV ATtiny20 178 Serial Programming Characteristics. Parameter Programming Voltage Clock Frequency Clock Period Clock Low Pulse Width Clock High Pulse Width Data Input to Clock High Setup Time Data Input Hold Time After Clock High Data Output Valid After Clock Low Time ...

Page 179

... CC L Additional Current Consumption for different I/O modules (absolute values 2V 1MHz CC 4 µA 5 µA 190 µA 3 µA 5 µA ATtiny20 = average switching frequency of SW “Power Reduction Register” on page 27 Typical numbers 4MHz 8MHz µA 110 µA 35 µ ...

Page 180

... PRTSPI PRTTWI 21.2 Current Consumption in Active Mode Figure 21-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ATtiny20 180 below can be used for calculating typical current consumption for other supply volt- Additional Current Consumption (percentage) in Active and Idle mode Current consumption additional to active mode with external clock ...

Page 181

... ACTIVE SUPPLY CURRENT vs. FREQUENCY 6 5,5 5 4,5 4 3,5 3 2,5 2 1,5 1 1 ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 4 3,5 3 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 Frequency [MHz] (Internal Oscillator, 8 MHz 3,5 4 4,5 VCC [V] ATtiny20 5.5 V 5.0 V 4 °C 25 °C -40 °C 5 181 ...

Page 182

... Figure 21-4. Active Supply Current vs. V Figure 21-5. Active Supply Current vs. V ATtiny20 182 CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 1 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 1 ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 KHz 0,12 0,1 0,08 0,06 0,04 0,02 0 1,5 2 2,5 3 (Internal Oscillator, 1 MHz) CC 3,5 4 4,5 5 VCC [V] (Internal Oscillator, 128 kHz) CC 3,5 4 4,5 5 VCC [V] 85 ° ...

Page 183

... Figure 21-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) Figure 21-7. Idle Supply Current vs. Frequency ( MHz) 8235B–AVR–04/11 IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0,12 0,1 0,08 0,06 0,04 0, 0,1 0,2 0,3 0,4 IDLE SUPPLY CURRENT vs. FREQUENCY 1,4 1,2 1 0,8 0,6 0,4 0,2 1 0,5 0,6 0,7 0,8 Frequency [MHz] 3 Frequency [MHz] ATtiny20 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0,9 1 5.5 V 5.0 V 4 183 ...

Page 184

... Figure 21-8. Idle Supply Current vs. V Figure 21-9. Idle Supply Current vs. V ATtiny20 184 CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 1 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 1 IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 0,25 0,2 0,15 0,1 0,05 0 1,5 2 2,5 3 (Internal Oscillator, 8 MHz) CC 3,5 4 4,5 5 VCC [V] (Internal Oscillator, 1 MHz) CC 3,5 4 4,5 5 VCC [V] 85 °C 25 ° ...

Page 185

... IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 KHz 0,03 0,025 0,02 0,015 0,01 0,005 0 1,5 2 2,5 3 POWER-DOWN SUPPLY CURRENT vs. V 0,45 0,4 0,35 0,3 0,25 0,2 0,15 0,1 0,05 0 1,5 2 2,5 3 (Internal Oscillator, 128 kHz) CC 3,5 4 4,5 5 VCC [V] (Watchdog Timer Disabled WATCHDOG TIMER DISABLED 3,5 4 4,5 5 VCC [V] ATtiny20 -40 °C -40 °C 25 °C 25 °C 85 °C 85 °C 5,5 85 °C 25 °C -40 °C 5,5 185 ...

Page 186

... Figure 21-12. Power-down Supply Current vs. V 21.5 Current Consumption in Reset Figure 21-13. Reset Supply Current vs. V ATtiny20 186 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1 Clock) RESET CURRENT vs. V EXCLUDING CURRENT THROUGH THE RESET PULLUP AND NO CLOCK ...

Page 187

... Figure 21-15. Analog Comparator Current vs. V 8235B–AVR–04/11 (at clk CC 450 400 350 300 250 200 150 100 50 0 1,5 2 2,5 3 ANALOG COMPARATOR CURRENT vs 1 250kHz) ADC ADC CURRENT vs 3 3 [V] CC ATtiny20 5,5 5,5 187 ...

Page 188

... Figure 21-16. Watchdog Timer Current vs. V Figure 21-17. Brownout Detector Current vs. V ATtiny20 188 WATCHDOG TIMER CURRENT vs 1,5 2 2,5 3 BROWNOUT DETECTOR CURRENT vs 1 3,5 4 4,5 5 VCC [ 3,5 4 4,5 5 VCC [V] -40 °C 25 °C 85 ° ...

Page 189

... I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 0,2 0,4 0,6 0,8 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ATtiny20 = 1.8V 1,2 1,4 1,6 1,8 VOP [V] = 2.7V VOP [V] 25 °C 85 °C -40 ° °C 85 °C -40 °C 3 189 ...

Page 190

... Figure 21-20. I/O pin Pull-up Resistor Current vs. Input Voltage (V Figure 21-21. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V ATtiny20 190 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 160 140 120 100 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE ...

Page 191

... RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 100 2.7V VRESET [ VRESET [V] ATtiny20 25 °C -40 °C 85 ° °C -40 °C 85 °C 6 191 ...

Page 192

... Output Driver Strength Figure 21-24. V Figure 21-25. V ATtiny20 192 : Output Voltage vs. Sink Current (I/O Pin I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 0,8 0,6 0,4 0 0 Output Voltage vs. Sink Current (I/O Pin I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 0,8 0,6 0,4 0 1.8V 1.8V CC 2,5 3 3,5 4 4,5 I [mA 3V ...

Page 193

... Output Voltage vs. Sink Current (I/O Pin I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 1 0,8 0,6 0,4 0 Output Voltage vs. Source Current (I/O Pin I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 1,9 1,8 1,7 1,6 1,5 1,4 1,3 1,2 1 ATtiny20 = 5V [mA 1.8V 1. [mA °C 85 °C 25 °C -40 °C 20 -40 ° ...

Page 194

... Figure 21-28. V Figure 21-29. V ATtiny20 194 : Output Voltage vs. Source Current (I/O Pin I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 3,2 3 2,8 2,6 2,4 2,2 2 1,8 1 Output Voltage vs. Source Current (I/O Pin I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 5,2 5 4,8 4,6 4,4 4 [mA 5V ...

Page 195

... RESET AS I/O OUTPUT VOLTAGE VS. SINK CURRENT 1 0,8 0,6 0,4 0 Output Voltage vs. Sink Current (Reset Pin as I/ RESET AS I/O OUTPUT VOLTAGE VS. SINK CURRENT 2 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 0 ATtiny20 = 1.8V) CC Vcc = 1. IOL [mA] = 3V) CC Vcc = IOL [mA] 85 °C 25 °C -40 ° °C 25 °C -40 °C 3 195 ...

Page 196

... Figure 21-32. V Figure 21-33. V ATtiny20 196 : Output Voltage vs. Sink Current (Reset Pin as I/ RESET AS I/O OUTPUT VOLTAGE VS. SINK CURRENT 2 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 0 0 Output Voltage vs. Source Current (Reset Pin as I/ RESET AS I/O OUTPUT VOLTAGE VS. SOURCE CURRENT 1,6 1,4 1,2 1 0,8 0,6 0,4 0 0,1 0,2 0,3 0,4 = 5V) CC Vcc = 5V 2,5 3 3,5 4 4,5 IOL [mA] = 1.8V CC Vcc = 1.8V 0,5 0,6 0,7 0,8 0,9 IOH [mA] 85 °C 25 ° ...

Page 197

... Output Voltage vs. Source Current (Reset Pin as I/ RESET AS I/O OUTPUT VOLTAGE VS. SOURCE CURRENT 3 2,5 2 1 0,2 0,4 0,6 : Output Voltage vs. Source Current (Reset Pin as I/ RESET AS I/O OUTPUT VOLTAGE VS. SOURCE CURRENT 4,5 4 3,5 3 2,5 2 1 0,2 0,4 0,6 CC Vcc = 3V 0,8 1 1,2 1,4 1,6 IOH [mA] CC Vcc = 5V 0,8 1 1,2 1,4 1,6 IOH [mA] ATtiny20 = 3V -40 °C 25 °C 85 °C 1 -40 °C 25 °C 85 °C 1,8 197 ...

Page 198

... Input Thresholds and Hysteresis Figure 21-36. V Figure 21-37. V ATtiny20 198 : Input Threshold Voltage vs I/O PIN INPUT THRESHOLD VOLTAGE vs. V 3,5 3 2,5 2 1,5 1 0,5 0 1 Input Threshold Voltage vs RESET INPUT THRESHOLD VOLTAGE vs. V 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 (I/O Pin, Read as ‘1’ VIH, IO PIN READ AS '1' 3,5 4 4,5 5 VCC [V] (I/O Pin, Read as ‘ ...

Page 199

... IH IL I/O PIN INPUT HYSTERESIS 0,6 -40 °C 0,5 25 °C 0,4 85 °C 0,3 0,2 0,1 0 1 Input Threshold Voltage vs RESET PIN AS I/O THRESHOLD VOLTAGE vs. V 3,5 3 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 (I/O Pin) CC 3 [V] CC (Reset Pin as I/O, Read as ‘1’ VIH, RESET READ AS '1' 3,5 4 4,5 5 VCC [V] ATtiny20 5,5 -40 °C 25 °C 85 °C 5,5 199 ...

Page 200

... Figure 21-40. V Figure 21-41. V ATtiny20 200 : Input Threshold Voltage vs RESET PIN AS I/O THRESHOLD VOLTAGE vs. V 2,5 2 1,5 1 0,5 0 1 Input Hysteresis vs RESET AS I/O INPUT HYSTERESIS 0,8 -40 °C 0,7 0,6 25 °C 0,5 85 °C 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 (Reset Pin as I/O, Read as ‘0’ VIL, RESET READ AS '0' 3,5 4 4,5 5 VCC [V] (Reset Pin as I/O) ...

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