ATtiny2313 Atmel Corporation, ATtiny2313 Datasheet - Page 10

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ATtiny2313

Manufacturer Part Number
ATtiny2313
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny2313

Flash (kbytes)
2 Kbytes
Pin Count
20
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
18
Ext Interrupts
18
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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The X-register, Y-
register, and Z-register
10
ATtiny2313
Figure 4. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in
Figure 5. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
X-register
Y-register
Z-register
Registers
Purpose
Working
General
Figure
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
4, each register is also assigned a data memory address, mapping them
7
XH
YH
ZH
0
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
0
0
0
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
Addr.
0x0D
0x0E
0x0F
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x00
0x01
0x02
0x10
0x11
Figure
5.
X-register High Byte
Y-register High Byte
Z-register High Byte
X-register Low Byte
Y-register Low Byte
Z-register Low Byte
XL
YL
ZL
0
2543L–AVR–08/10
0
0
0
0
0

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