ATtiny24 Atmel Corporation, ATtiny24 Datasheet
ATtiny24
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... On-chip Temperature Sensor • I/O and Packages – Available in 20-Pin QFN/MLF & 14-Pin SOIC and PDIP – Twelve Programmable I/O Lines • Operating Voltage: – 1.8 – 5.5V for ATtiny24V/44V/84V – 2.7 – 5.5V for ATtiny24/44/84 • Speed Grade – ATtiny24V/44V/84V • 0 – 4 MHz @ 1.8 – 5.5V • 0 – 10 MHz @ 2.7 – 5.5V – ...
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... Pin Configurations Figure 1-1. Pinout ATtiny24/44/84 (PCINT8/XTAL1/CLKI) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 (ADC4/USCK/SCL/T1/PCINT4) PA4 (ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1 (ADC0/AREF/PCINT0) PA0 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 Pin Descriptions 1 ...
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... Port B also serves the functions of various special features of the ATtiny24/44/84 as listed in Section 10.2 “Alternate Port Functions” on page 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The min- imum pulse length is given in generate a reset ...
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... Overview ATtiny24/44/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. VCC GND The AVR core combines a rich instruction set with 32 general purpose working registers ...
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... ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface conventional non-volatile memory programmer on-chip boot code running on the AVR core. The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits. 8006K–AVR–10/10 ...
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... Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. ATtiny24/44/84 6 8006K–AVR–10/10 ...
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... The Program memory is In-System Reprogrammable Flash memory. 8006K–AVR–10/10 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATtiny24/44/84 Data Bus 8-bit Status and Control General Purpose Interrupt Registrers Unit Watchdog Timer ALU ...
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... This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. ATtiny24/44/84 8 8006K–AVR–10/10 ...
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... Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8006K–AVR–10/ R/W R/W R/W R ⊕ V ATtiny24/44/ R/W R/W R/W R SREG 9 ...
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... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in ATtiny24/44/84 10 below shows the structure of the 32 general purpose working registers in the CPU. ...
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... SP15 SP14 SP13 SP12 SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R/W RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND ATtiny24/44/ R26 (0x1A R28 (0x1C R30 (0x1E SP11 SP10 SP9 SP8 SP3 SP2 SP1 SP0 R/W R/W R/W ...
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... The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address the higher is the ATtiny24/44/ directly generated from the selected clock source for the ...
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... EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ Note: 8006K–AVR–10/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) See “Code Examples” on page 6. ATtiny24/44/84 13 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny24/44/ set Global Interrupt Enable See “ ...
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... The ATtiny24/44/84 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are bits wide, the Flash is organized as 1024/2048/4096 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny24/44/84 Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program memory locations. ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data SRAM in the ATtiny24/44/84 are all accessible through all these addressing modes. The Register File is described in Figure 5-2. ...
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... Table 5-1 on page 22. The EEPE bit remains set until the erase and write opera- Table 5-1 on page 22). The EEPE bit remains set until the erase operation ATtiny24/44/84 Table 5-1 on page 22. A self-timing func- for details on how to avoid “Split Byte Programming” on page 17 Table 5-1 on page 22) ...
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... Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } Note: ATtiny24/44/84 18 r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; See “Code Examples” on page 6. “OSCCAL – Oscillator Calibration Register” on 8006K–AVR–10/10 ...
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... Set up address register */ EEAR = ucAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; See “Code Examples” on page 6. , the EEPROM data can be corrupted because the supply voltage is CC ATtiny24/44/84 reset protection circuit can CC 19 ...
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... I/O Memory The I/O space definition of the ATtiny24/44/84 is shown in All ATtiny24/44/84 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions ...
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... Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read ATtiny24/44/84. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny24/44/84 and will always read as zero. • ...
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... The user should poll the EEPE bit before starting the read opera- tion write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. ATtiny24/44/84 22 EEPROM Programming Mode Bits and Programming Times EEPM0 ...
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... Read/Write Initial Value 8006K–AVR–10/ MSB R/W R/W R/W R MSB R/W R/W R/W R MSB R/W R/W R/W R ATtiny24/44/ LSB R/W R/W R/W R LSB R/W R/W R/W R LSB R/W R/W R/W R GPIOR2 GPIOR1 GPIOR0 ...
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... Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. ATtiny24/44/84 24 presents the principal clock systems in the AVR and their distribution. All of the clocks 33 ...
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... Device Clocking Options Select page 26) page page 27) page 28) page 1. For all fuses “1” means unprogrammed and “0” means programmed. Number of Watchdog Oscillator Cycles Typ Time-out ATtiny24/44/84 CKSEL3:0 26) 28) Table Number of Cycles 512 8K (8,192) (1) 0000 0001 0010 0011 0100 ...
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... This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6-4. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically cal- ATtiny24/44/84 26 26. To run the device on an external clock, the CKSEL Fuses must be programmed to External Clock Drive Configuration ...
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... Start-up Time from Power-down the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + ensure programming mode can be entered. ATtiny24/44/84 “OSCCAL – Oscillator Calibration Register” on Table 20-2 on page 162. Nominal Frequency 8.0 MHz Additional Delay from Reset ( ...
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... Some initial guidelines for choosing capacitors for use with crystals are given in given by the manufacturer should be used. ATtiny24/44/84 28 Figure 6-3. To find suitable capacitors please consult the manufacturer’s datasheet. ...
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... These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. ATtiny24/44/84 Recommended C1 and C2 Value (pF) – ...
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... For low-voltage devices (ATtiny24V/44V/84V) it should be noted that unprogramming the CKDIV8 fuse may result in overclocking. At low voltages (below 2.7V) the devices are rated for maximum 4 MHz operation (see internal oscillator directly to the system clock line will run the device at 8 MHz ...
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... CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. • Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock ...
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... The device is shipped with the CKDIV8 Fuse programmed. Table 6-11. CLKPS3 ATtiny24/44/84 32 Clock Prescaler Select CLKPS2 CLKPS1 ...
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... MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 24 ATtiny24/44/84. The figure is helpful in selecting an appropriate sleep mode. the different sleep modes and their wake up sources. Table 7-1. Sleep Mode Idle ...
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... Stand-By, while writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active. Writing to the BODS bit is controlled by a timed sequence and an enable bit, see MCU Control Register” on page ATtiny24/44/84 34 130. This will reduce power consumption in Idle level has dropped during the sleep period. ...
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... Limitations BOD disable functionality has been implemented in the following devices, only: • ATtiny24, revision E, and newer • ATtiny44, revision D, and newer • ATtiny84, revision B, and newer Revisions are marked on the device package and can be located as follows: • Bottom side of packages 14P3 and 14S1 • ...
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... Bit 7 – BODS: BOD Sleep BOD disable functionality is available in some devices, only. See In order to disable BOD during sleep (see logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First, ATtiny24/44/84 36 “Brown-out Detection” on page 41 for details on how to configure the Brown-out Detector. ...
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... Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. • Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. ...
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... USI again, the USI should be re initialized to ensure proper operation. • Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot be used when the ADC is shut down. ATtiny24/44/84 38 8006K–AVR–10/10 ...
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... Electrical parameters of the Table 20-4 on page 177. Reset Logic Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock CK Generator CKSEL[3:0] SUT[1:0] ATtiny24/44/84 DATA BUS MCU Status Register (MCUSR) Delay Counters TIMEOUT “Clock Sources” on page 25. 39 ...
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... Reset Sources The ATtiny24/44/84 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled. ...
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... Figure 8-4. 8.2.3 Brown-out Detection ATtiny24/44/84 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny24/44/84 resets and executes from the Reset Vec- tor. For timing details on the Watchdog Reset, refer to ...
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... Level State 1 Disabled 2 Enabled Watchdog Timer 128 kHz OSCILLATOR WATCHDOG RESET WDP0 WDP1 WDP2 WDP3 WDE ATtiny24/44/84 Table 8-1 for details. How to Disable the How to Change Time- WDT out Timed sequence No limitations Always enabled Timed sequence WATCHDOG PRESCALER MUX MCU RESET See “ ...
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... C Code Example void WDT_off(void) { _WDR(); /* Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; } Note: ATtiny24/44/84 44 r16, (0<<WDRF) MCUSR, r16 r16, WDTCSR See “Code Examples” on page 6. 8006K–AVR–10/10 ...
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... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
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... To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Note: ATtiny24/44/84 46 Watchdog Timer Configuration WDIE Watchdog Timer State ...
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... If selected, one of the valid settings below 0b1010 will be used. ATtiny24/44/84 Typical Time-out at Cycles cycles cycles cycles 64 ms 16K cycles 0.125 s 32K cycles 0.25 s 64K cycles 0.5 s 128K cycles 1.0 s 256K cycles 2 ...
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... If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general setup for Reset and Interrupt Vector Addresses in ATtiny24/44/84 is shown in the program example below. ATtiny24/44/84 48 Reset and Interrupt Vectors ...
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... Main program start out SPH,r16 ldi r16, low(RAMEND) out SPL,r16 sei <instr> ... “Clock Sources” on page ATtiny24/44/84 Comments ; Reset Handler ; IRQ0 Handler ; PCINT0 Handler ; PCINT1 Handler ; Watchdog Interrupt Handler ; Timer1 Capture Handler ; Timer1 Compare A Handler ; Timer1 Compare B Handler ; Timer1 Overflow Handler ...
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... SLEEP command. 9.2.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 9-1. PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF ATtiny24/44/84 50 24. Timing of pin change interrupts pin_lat pcint_in_( pin_sync LE clk PCINT(0) in PCMSK(x) clk Figure 9-1 ...
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... Initial Value • Bits 7, 3:0 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...
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... Read/Write Initial Value • Bits 7, 3:0 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor- responding Interrupt Vector ...
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... If PCINT7:0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8006K–AVR–10/ PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATtiny24/44/ PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK0 53 ...
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... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATtiny24/44/84 54 and Ground as indicated in CC for a complete list of parameters. ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 67, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATtiny24/44/84 Figure 10-2 PUD Q D DDxn Q ...
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... The maximum and minimum propagation delays are denoted t Figure 10-3. Synchronization when Reading an Externally Applied Pin value ATtiny24/44/84 56 summarizes the control signals for the pin value. Port Pin Configurations ...
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... Two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. ATtiny24/44/84 0xFF nop in r17, PINx ...
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... Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. In below is shown how the port pin control signals from the simplified be overridden by alternate functions. ATtiny24/44/84 58 See “Code Examples” on page 6. Figure 10-2 on page 55, the digital input signal can be clamped to ground at the “ ...
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... SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATtiny24/44/84 PUD Q D DDxn ...
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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATtiny24/44/84 60 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ...
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... PA6 MOSI: SPI Master Data Output / Slave Data Input OC1A: Timer/Counter1 Compare Match A Output PCINT6: Pin Change Interrupt 0, Source 6 ADC7: ADC Input Channel 7 OC0B: Timer/Counter0 Compare Match B Output PA7 ICP1: Timer/Counter1 Input Capture Pin PCINT7: Pin Change Interrupt 0, Source 7 ATtiny24/44/84 Table 10- ...
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... Timer/Counter1 Compare Match B. The PA5 pin has to be configured as an output (DDA5 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. • PCINT5: Pin Change Interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change interrupt 0. ATtiny24/44/ ...
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... OC0B 0 0 USISIE + (PCINT6 • PCINT7 • PCIE0 + ADC7D PCIE0) + ADC6D PCINT7 • PCIE0 USISIE + PCINT7 • PCIE0 PCINT7/ICP1 Input DI/SDA/PCINT6 Input ADC7 Input ADC6 Input ATtiny24/44/ PA5/ADC5/MISO/DO/ OC1B/ PCINT5 (USIWM1 • USIWM0) + OC1B enable USIWM1 • USIWM0 • (USIWM1 + USIWM0) • ...
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... PVOV PTOE DIEOE DIEOV DI AIO Table 10-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny24/44/84 64 Overriding Signals for Alternate Functions in PA4:PA2 PA4/ADC4/USCK/SCL/T1/ PCINT4 PA3/ADC3/T0/PCINT3 USIWM1 0 USI_SCL_HOLD + 0 PORTA4) • DDA4 USIWM1 • DDA4 USI_PTOE ...
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... XTAL2: Crystal Oscillator Output PB1 PCINT9: Pin Change Interrupt 1, Source 9 INT0: External Interrupt 0 Input OC0A: Timer/Counter0 Compare Match A output PB2 CKOUT: System Clock Output PCINT10:Pin Change Interrupt 1, Source 10 RESET: Reset pin PB3 dW: debugWire I/O PCINT11:Pin Change Interrupt 1, Source 11. ATtiny24/44/84 Table 10-7. “External Clock” on page 26. 65 ...
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... Table 10-8 on page 66 overriding signals shown in Table 10-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 1. 2. ATtiny24/44/84 66 and Table 10-9 on page 67 Figure 10-5 on page Overriding Signals for Alternate Functions in PB3:PB2 RESET/dW/ PB3/ PCINT11 (1) RSTDISBL + DEBUGWIRE_ENABLE 1 (1) RSTDISBL + DEBUGWIRE_ENABLE (2) DEBUGWIRE_ENABLE • debugWire ...
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... R for more details about this feature PORTA7 PORTA6 PORTA5 R/W R/W R DDA7 DDA6 DDA5 R/W R/W R ATtiny24/44/84 PB0/XTAL1/PCINT8 (2) (1) EXT_CLOCK + EXT_OSC 0 (2) (1) EXT_CLOCK + EXT_OSC 0 (2) (1) EXT_CLOCK + EXT_OSC 0 0 (2) (1) EXT_CLOCK + EXT_OSC + (PCINT8 • PCIE1) (2) ( EXT_CLOCK • PWR_DOWN ) + (2) (1) (EXT_CLOCK • ...
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... PORTB – Port B Data Register Bit 0x18 (0x38) Read/Write Initial Value 10.3.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial Value 10.3.7 PINB – Port B Input Pins Bit 0x16 (0x36) Read/Write Initial Value ATtiny24/44/ PINA7 PINA6 PINA5 PINA4 R/W R/W R/W R/W N/A N/A N/A ...
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... Description” on page Count Clear Control Logic Direction TOP BOTTOM Timer/Counter TCNTn = = OCRnA Fixed TOP Value = OCRnB TCCRnA TCCRnB ATtiny24/44/84 Figure 11-1 on page 2. CPU accessible I/O Registers, 80. TOVn (Int.Req.) Clock Select clk Tn Edge Detector ( From Prescaler ) = 0 OCnA (Int.Req.) Waveform Generation OCnB (Int.Req.) ...
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... Timer/Counter Control Register (TCCR0B). For details on clock sources and pres- caler, see 11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 11-2 on page 71 ATtiny24/44/84 70 “Output Compare Unit” on page 71 Table 11-1 are also used extensively throughout the document. Definitions ...
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... Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 74. ATtiny24/44/84 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
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... Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 ATtiny24/44/84 72 shows a block diagram of the Output Compare unit. ...
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... Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi- ble on the pin. The port override function is independent of the Waveform Generation mode. 8006K–AVR–10/10 Waveform Generator I/O ATtiny24/44/84 Figure 11-4 on page OCnx 0 ...
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... OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. ATtiny24/44/84 74 “Register Description” on page 80 Table 11-2 on page Table 11-4 on page “ ...
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... PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited 8006K–AVR–10/10 Figure 11-5 on page clk_I ------------------------------------------------- - OCnx ⋅ ⋅ ATtiny24/44/84 75. The counter value OCnx Interrupt Flag Set (COMnx1 OCRnx /2 clk_I/O 75 ...
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... The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result ATtiny24/44/84 76 Figure 11-6 on page 76 ...
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... TCNTn OCn OCn Period 8006K–AVR–10/ when OCR0A is set to zero. This fea- 0 clk_I/O 77. The TCNT0 value is in the timing diagram shown as a histogram for 1 2 ATtiny24/44/84 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 (COMnx1 ...
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... The Timer/Counter is a synchronous design and the timer clock (clk clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. The figure shows the count sequence close to the MAX value in all modes other than phase cor- rect PWM mode. ATtiny24/44/84 78 Table 11-4 on page f OCnxPCPWM ...
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... MAX - 1 MAX shows the setting of OCF0B in all modes and OCF0A in all modes OCRnx - 1 OCRnx OCRnx Value shows the setting of OCF0A and the clearing of TCNT0 in CTC mode ATtiny24/44/84 BOTTOM BOTTOM + 1 /8) clk_I/O BOTTOM BOTTOM + 1 /8) ...
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... When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 11-2. COM0A1 Table 11-3 ATtiny24/44/84 80 caler (f /8) clk_I/O TOP - 1 TOP ...
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... COM0B1:0 bit functionality when the WGM02:0 bits Compare Output Mode, non-PWM Mode COM0B0 Description 0 Normal port operation, OC0B disconnected. 1 Toggle OC0B on Compare Match 0 Clear OC0B on Compare Match 1 Set OC0B on Compare Match ATtiny24/44/84 (1) “Fast PWM Mode” on (1) “Phase Correct PWM Mode” ...
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... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. • Bits 1:0 – WGM01, WGM00: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- ...
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... MAX = 0xFF BOTTOM = 0x00 FOC0A FOC0B – ATtiny24/44/84 Timer/Counter Update of Mode of Operation TOP OCRx at Normal 0xFF Immediate PWM, Phase 0xFF TOP Correct CTC OCRA Immediate Fast PWM 0xFF BOTTOM Reserved – PWM, Phase ...
Page 84
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02, CS01, CS00: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 85
... Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 86
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. See “Waveform Generation Mode Bit Description” on page ATtiny24/44/84 86 Table 11-8 on page 83 83. ...
Page 87
... I/O pins, refer to Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 12-1. 16-bit Timer/Counter Block Diagram 8006K–AVR–10/10 “Pinout ATtiny24/44/84” on page “Register Description” on page Count Clear Control Logic ...
Page 88
... The following definitions are used extensively throughout the section: Table 12-1. Constant BOTTOM MAX TOP ATtiny24/44/84 88 92. The compare match event will also set the Compare Match 129). The Input Capture unit includes a digital filtering unit (Noise Definitions Description The counter reaches BOTTOM when it becomes 0x00 ...
Page 89
... Prescaler” on page shows a block diagram of the counter and its surroundings. DATA BUS (8-bit) TEMP (8-bit) Count TCNTnL (8-bit) Clear Direction TCNTn (16-bit Counter) ATtiny24/44/84 115. TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) ...
Page 90
... The Input Capture unit is illustrated by the block diagram shown in elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. ATtiny24/44/84 90 Increment or decrement TCNT1 by 1. ...
Page 91
... Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog 8006K–AVR–10/10 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) ACO* ACIC* Analog Comparator 105. ATtiny24/44/84 (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge Canceler Detector “Accessing 16-bit Registers” ...
Page 92
... Alternatively the OCF1x flag can be cleared by software by writ- ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode ATtiny24/44/84 92 (Figure 13-1 on page 115). The edge detector is also ...
Page 93
... DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) TOP Waveform Generator BOTTOM WGMn3:0 ATtiny24/44/84 96). TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCFnx (Int.Req.) OCnx COMnx1:0 93 ...
Page 94
... PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin system reset occur, the OC1x Register is reset to “0”. ATtiny24/44/84 94 105. “Accessing 16-bit Registers” ...
Page 95
... For non-PWM modes, the action can be forced to have immediate effect by using the 1x strobe bits. 8006K–AVR–10/10 Waveform D Q Generator OCnx D Q PORT D Q DDR Table 12-2 on page for details. “Register Description” on page 108 Table 12-2 on page 109. For fast PWM mode refer to ATtiny24/44/84 1 OCnx Pin 0 109, Table 12-3 on page 109 Table 12-3 on Table 12 ...
Page 96
... It also simplifies the opera- tion of counting external events. The timing diagram for the CTC mode is shown in (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. ATtiny24/44/84 96 94) “Timer/Counter Timing Diagrams” on page Figure 12-6 on page 103 ...
Page 97
... PWM mode well suited for power regulation, rectification, and DAC 8006K–AVR–10/ when OCR1A is set to zero (0x0000). The waveform frequency is defined 1 A clk_I --------------------------------------------------- ⋅ OCnA 2 N ATtiny24/44/84 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 97 ...
Page 98
... Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low ATtiny24/44/ log ...
Page 99
... In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. 8006K–AVR–10/10 ATtiny24/44/84 Table 12-3 on page f clk_I/O f ...
Page 100
... Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in ATtiny24/44/84 100 ( ) ...
Page 101
... The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and 8006K–AVR–10/10 f OCnxPCPWM and Figure 12-9 on page 102). ATtiny24/44/84 Table 12-4 on page f clk_I/O = --------------------------- - ⋅ ⋅ TOP 109) ...
Page 102
... Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 12-9 on page 102 mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. ATtiny24/44/84 102 ( TOP log R ...
Page 103
... Figure 12-11 on page 104 8006K–AVR–10/10 f clk_I --------------------------- - OCnxPFCPWM ⋅ TOP Figure 12-10 shows a timing diagram for the setting of OCF1x. OCRnx - 1 OCRnx OCRnx Value shows the same timing data, but with the prescaler enabled. ATtiny24/44/84 Table 12-4 on ⋅ therefore shown OCRnx + 1 OCRnx + 2 103 ...
Page 104
... TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICFn as TOP) OCRnx (Update at TOP) Figure 12-13 on page 105 ATtiny24/44/84 104 OCRnx - 1 OCRnx shows the count sequence close to TOP in various modes. When I/O Tn /1) I/O TOP - 1 TOP - 1 (FPWM) (if used Old OCRnx Value shows the same timing data, but with the prescaler enabled ...
Page 105
... OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. 8006K–AVR–10/10 clk I/O clk Tn /8) I/O TOP - 1 TOP - 1 (FPWM) (if used Old OCRnx Value ATtiny24/44/84 /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value TOP - 2 105 ...
Page 106
... Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret ATtiny24/44/84 106 See “Code Examples” on page 6. 8006K–AVR–10/10 ...
Page 107
... Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; See “Code Examples” on page 6. ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret ATtiny24/44/84 107 ...
Page 108
... OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). ATtiny24/44/84 108 See “Code Examples” on page 6 ...
Page 109
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 99 ATtiny24/44/84 Description Normal port operation, OC1A/OC1B disconnected. Toggle OC1A/OC1B on Compare Match. Clear OC1A/OC1B on Compare Match (Set output to low level). Set OC1A/OC1B on Compare Match (Set output to high level) ...
Page 110
... This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. ATtiny24/44/84 110 Table 12-5 on page ...
Page 111
... I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – ATtiny24/44/ – – – – Figure 0 – ...
Page 112
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16- bit registers. See ATtiny24/44/84 112 7 6 ...
Page 113
... Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “ ...
Page 114
... Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13 used as the TOP value, the ICF1 flag is set when the coun- ter reaches the TOP value ...
Page 115
... CLK_I Synchronization pulse for each positive (CSn2 negative (CSn2 < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ATtiny24/44/84 /8, f /64, f /256, or CLK_I/O CLK_I/O CLK_I/O ). The Tn Figure 13-1 shows a functional ). The latch is transparent in the clk I/O Tn_sync ...
Page 116
... Timer/Counter start counting. • Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. ATtiny24/44/84 116 Clear Synchronization 1. The synchronization logic on the input pins ( ...
Page 117
... The most significant bit of the USI Data Register is connected to one of two output pins (depend- ing on the mode configuration, see transparent latch between the output of the USI Data Register and the output pin, which delays 8006K–AVR–10/10 “Pinout ATtiny24/44/84” on page “Register Descriptions” on page 3 2 ...
Page 118
... The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORTA register or by writing a one to bit USITC bit in USICR. ATtiny24/44/84 118 Bit7 Bit6 ...
Page 119
... Figure 14-3 (Figure 14-3), a bus transfer involves the following steps: out USIDR,r16 ldi r16,(1<<USIOIF) out USISR,r16 ldi r17,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) ATtiny24/44/ LSB LSB At the top of the figure is a USCK cycle ref- 8 ...
Page 120
... The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI as an SPI master with maximum speed ( SCK CK SPITransfer_Fast: ret ATtiny24/44/84 120 out USICR,r17 in r16, USISR sbrs r16, USIOIF rjmp ...
Page 121
... PORTA register. 8006K–AVR–10/10 ldi r16,(1<<USIWM0)|(1<<USICS1) out USICR,r16 out USIDR,r16 ldi r16,(1<<USIOIF) out USISR,r16 in r16, USISR sbrs r16, USIOIF rjmp SlaveSPITransfer_loop in r16,USIDR ret shows two USI units operating in two-wire mode, one as master and one as slave. It ATtiny24/44/84 121 ...
Page 122
... In addition, the start detector will hold the SCL line low after the master has forced a negative edge on this line (B). This allows the slave to wake up from sleep or complete other tasks before setting up the USI Data Register to receive the address. This is done by clearing the start condition flag and resetting the counter. ATtiny24/44/84 122 Bit7 Bit6 ...
Page 123
... Figure 14-6. The SDA line is delayed (in the range of 50 SDA SCL Write( USISIF) 25) must also be taken into consideration. Refer to the description page 125 for further details This is also the maximum data transmit and CK ATtiny24/44/84 USISIF CLOCK HOLD CLR CLR 123 ...
Page 124
... The output will be changed immediately when a new MSB is written as long as the latch is open. Note that the Data Direction Register bit corresponding to the output pin must be set to one in order to enable data output from the USI Data Register. ATtiny24/44/84 124 7 6 ...
Page 125
... These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. 8006K–AVR–10/ MSB USISIF USIOIF USIPF USIDC R/W R/W R ATtiny24/44/ LSB USICNT3 USICNT2 USICNT1 USICNT0 R/W R/W R/W R USIBR USISR ...
Page 126
... Basically, only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked externally and data input sampled, even when outputs are disabled. ATtiny24/44/84 126 7 6 ...
Page 127
... Counter Overflow Flag (USIOIF) is cleared. 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation. ATtiny24/44/84 (1) . USI Data Register or the corresponding bit in ...
Page 128
... USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. The bit will read as zero. ATtiny24/44/84 128 shows the relationship between the USICS1:0 and USICLK setting and clock source ...
Page 129
... See Table 15-1 on page 129. and Table 10-9 on page 67 Analog Comparator Multiplexed Input ADEN MUX4:0 X XXXXX 1 XXXXX 0 00000 0 00001 0 00010 0 00011 ATtiny24/44/84 for Analog Comparator pin placement. Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ACIC To T/C1 Capture Trigger MUX Table 129 ...
Page 130
... Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection ATtiny24/44/84 130 Analog Comparator Multiplexed Input (Continued) ...
Page 131
... Comparator Interrupt on Rising Output Edge BIN ACME – ADLAR R/W R “Analog Comparator Multiplexed Input” on page ADC7D ADC6D ADC5D ADC4D R/W R/W R/W R ATtiny24/44/ – ADTS2 ADTS1 ADTS0 R R/W R/W R 129 ADC3D ADC2D ADC1D ADC0D R/W R/W R/W R ...
Page 132
... Input Polarity Reversal Mode 16.2 Overview The ATtiny24/44/84 features a 10-bit successive approximation ADC. The ADC is connected to 8-pin port A for external sources. In addition to external sources internal temperature sensor can be measured by ADC. Analog Multiplexer allows eight single-ended channels or 12 differential channels from Port A. The programmable gain stage provides ampification steps 0 dB (1x) and 26 dB (20x) for 12 differential ADC channels ...
Page 133
... TEMPERATURE SENSOR ADC8 AGND SINGLE ENDED / DIFFERENTIAL SELECTION POS. INPUT MUX + - GAIN AMPLIFIER NEG. INPUT MUX ATtiny24/44/84 ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS 15 ADC CTRL. & STATUS A ADC DATA REGISTER REGISTER (ADCSRA) (ADCH/ADCL) TRIGGER SELECT PRESCALER CONVERSION LOGIC SAMPLE & HOLD ...
Page 134
... Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. ATtiny24/44/84 134 8006K–AVR–10/10 ...
Page 135
... MHz. Figure 16-3. ADC Prescaler 8006K–AVR–10/10 ADTS[2:0] ADIF SOURCE EDGE DETECTOR SOURCE n ADSC ADEN Reset START CK ADPS0 ADPS1 ADPS2 ATtiny24/44/84 PRESCALER START ADATE CONVERSION LOGIC 7-BIT ADC PRESCALER ADC CLOCK SOURCE CLK ADC 135 ...
Page 136
... ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. Figure 16-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL ATtiny24/44/84 136 Figure 16-4 below. First Conversion ...
Page 137
... Sample & Prescaler Hold Reset MUX and REFS Update Figure One Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete ATtiny24/44/84 One Conversion Conversion Complete 16-7. Next Conversion Sign and MSB of Result LSB of Result Sample & ...
Page 138
... In Free Running mode, always select the channel before starting the first conversion. The chan- nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel ATtiny24/44/84 138 Table 16-1 ...
Page 139
... ADC. 8006K–AVR–10/10 REF will result in codes close to 0x3FF. V REF , or internal 1.1V reference, or external AREF pin. The first ADC conversion result CC ATtiny24/44/84 ) indicates the conversion range for the ADC. Single REF Figure 16-8 on page /2) should not be present to avoid ADC can be selected as 140 ...
Page 140
... ADC Noise Reduction Mode 16.10 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior, as follows: ATtiny24/44/84 140 I IH ADCn ...
Page 141
... Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 16-10. Gain Error Output Code 8006K–AVR–10/10 Offset Error ATtiny24/44/84 Ideal ADC Actual ADC V Input Voltage REF Gain Error ...
Page 142
... Figure 16-11. Integral Non-linearity (INL) Output Code • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 16-12. Differential Non-linearity (DNL) ATtiny24/44/84 142 Output Code 0x3FF 1 LSB ...
Page 143
... The voltage of the positive pin must always be larger ( V POS ADC ---------------------------------------------------- - GAIN = is the voltage on the positive input pin, V POS the selected voltage reference. The result is presented in two’s complement form, from ATtiny24/44/84 ⋅ V 1024 IN = -------------------------- V REF the selected voltage reference (see REF 146) ...
Page 144
... ADCH and ADCL are the ADC data registers the fixed slope coefficient and T temperature sensor offset. Typically very close to 1.0 and in single-point calibration the coefficient may be omitted. Where higher accuracy is required the slope coefficient should be evaluated based on measurements at two temperatures. ATtiny24/44/84 144 Temperature vs. Sensor Output Voltage (Typical Case) -40°C ...
Page 145
... PA0 (AREF External voltage reference at PA0 (AREF) pin, internal reference turned off 0 Internal 1.1V voltage reference 1 Reserved show values for single endid channels and where the differential channels as well as Table 16-4 on page 146 ATtiny24/44/ MUX3 MUX2 MUX1 R/W R/W ...
Page 146
... For normal differential channel pairs MUX5 bit work as a polarity reversal bit. Toggling of the MUX5 bit exhanges the positive and negative channel other way a round. Table 16-5. Positive Differential Input ADC0 (PA0) ADC1 (PA1) ATtiny24/44/84 146 Single-Ended Input channel Selections. (1) (2) (4) (1) 1 ...
Page 147
... ADC3 (PA3) ADC6 (PA6) ADC7 (PA7) For offset calibration, only. See “Operation” on page “Operation” on page 133 ADEN ADSC ADATE R/W R/W R ATtiny24/44/84 MUX5:0 Gain 1x 101100 010000 101010 101110 110000 (1) 100100 010010 010100 010110 011000 110010 011010 110100 111010 011100 ...
Page 148
... When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter- rupt is activated. • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 16-6. ADPS2 ATtiny24/44/84 148 ADC Prescaler Selections ADPS1 ...
Page 149
... BIN ACME – ADLAR R/W R/W R/W R ATtiny24/44/ – – ADC9 ADC8 ADC3 ADC2 ADC1 ADC0 ...
Page 150
... Bit 3 – Res: Reserved Bit This bit is reserved bit in the ATtiny24/44/84 and will always read as what was wrote there. • Bits 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion ...
Page 151
... The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. Figure 17-1. The debugWIRE Setup 8006K–AVR–10/10 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator dW dW(RESET) GND ATtiny24/44/84 1.8 - 5.5V VCC 151 ...
Page 152
... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATtiny24/44/84 152 will not work. CC ® ...
Page 153
... Page Write operation or by writing the CTPB bit in SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. 8006K–AVR–10/10 The CPU is halted during the Page Erase operation. ATtiny24/44/84 153 ...
Page 154
... The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 18-1. Addressing the Flash During SPM Z - REGISTER Note: ATtiny24/44/84 154 The CPU is halted during the Page Write operation ...
Page 155
... And Data Memory Lock Bits” on page 159 FLB7 FLB6 FLB5 Table 19-5 on page 161 for a detailed description and mapping of the Fuse Low Byte. ATtiny24/44/84 page 161 – – – LB2 for more information ...
Page 156
... Preload SPMCSR bits into R16, then write to SPMCSR ldi out SPMCSR, r16 ; Issue LPM. Table data will be returned into r17 lpm r17, Z ret Note: ATtiny24/44/84 156 FHB7 FHB6 FHB5 Table 19-4 on page 160 for detailed description and mapping of the Fuse High Byte. ...
Page 157
... Program memory operations. Bit 0x37 (0x57) Read/Write Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved in the ATtiny24/44/84 and will always read as zero. 8006K–AVR–10/10 161. , the Flash program can be corrupted because the supply voltage is CC (1) ...
Page 158
... SPM instruction SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. ATtiny24/44/84 158 “Device Signature Imprint Table” on page 161 “EEPROM Write Prevents Writing to SPMCSR” on page 155 for for details ...
Page 159
... This section describes the different methods for programming ATtiny24/44/84 memories. 19.1 Program And Data Memory Lock Bits The ATtiny24/44/84 provides two lock bits which can be left unprogrammed (“1”) or can be pro- grammed (“0”) to obtain the additional security listed in erased to “1” with the Chip Erase command. ...
Page 160
... Fuse Bytes The ATtiny24/44/84 have three fuse bytes. describe the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 19-3. Fuse Extended Byte SELFPRGEN Notes: Table 19-4 ...
Page 161
... Calibration data for internal oscillator (1) Signature byte 1 Reserved for internal use (1) Signature byte 2 Reserved for internal use 1. See section “Signature Bytes” for more information. 2. See section “Calibration Byte” for more information. ATtiny24/44/84 Default Value 0 (programmed) 1 (unprogrammed) 1 (unprogrammed) 0 (programmed) 0 (programmed) 0 (programmed) 1 (unprogrammed) 0 (programmed) for details ...
Page 162
... ATtiny44 ATtiny84 19.3.2 Calibration Byte The device signature imprint table of ATtiny24/44/84 contains one byte of calibration data for the internal oscillator, as shown in written into the OSCCAL register to ensure correct frequency of the calibrated oscillator. Calibration bytes can also be read by the device firmware. See section Signature Data from Software” ...
Page 163
... Pins MOSI PA6 MISO PA5 SCK PA4 In Table 19-10 above, the pin mapping for SPI programming is listed. Not all devices use the SPI pins dedicated for the internal SPI interface. ATtiny24/44/84 +1.8 - 5.5V VCC I/O Description I Serial Data in O Serial Data out I Serial Clock 163 ...
Page 164
... High:> 2 CPU clock cycles for f 19.5.1 Serial Programming Algorithm When writing serial data to the ATtiny24/44/84, data is clocked on the rising edge of SCK. When reading, data is clocked on the falling edge of SCK. See details. To program and verify the ATtiny24/44/84 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in 1 ...
Page 165
... MSB $20 adr MSB $A0 $00 $58 $00 $30 $00 $50 $00 $58 $08 $50 $08 $38 $00 ATtiny24/44/84 Minimum Wait Delay 4.5 ms 4.0 ms 9.0 ms 4.5 ms and Figure 19-2 on page 166. Instruction Format Byte 3 $00 $00 $00 data byte out Extended adr adr LSB high data byte in adr LSB low data byte in ...
Page 166
... See http://www.atmel.com/avr for Application Notes regarding programming and programmers. Figure 19-2. Serial Programming Instruction example Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Adr Bit 15 B ATtiny24/44/84 166 Byte 1 $4C $C0 $C2 $AC $AC $AC $AC ...
Page 167
... After data is loaded to the page buffer, program the EEPROM page, see 166. 19.6 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data mem- ory, Lock bits and Fuse bits in the ATtiny24/44/84. Figure 19-3. High-voltage Serial Programming Table 19-13. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode ...
Page 168
... High-Voltage Serial Programming Algorithm To program and verify the ATtiny24/44/84 in the High-voltage Serial Programming mode, the fol- lowing sequence is recommended (See instruction formats in 19.7.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed ...
Page 169
... Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny24/44/84, data is clocked on the rising edge of the serial clock, see page 184 8006K–AVR–10/10 Table 19-16 on page 1 ...
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... Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Program- ming” cycle to finish. 4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. ATtiny24/44/84 170 PCMSB PAGEMSB PROGRAM ...
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... Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in page 171. 19.7.10 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII ...
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... Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Instr.1/5 SDI 0_0000_0010_00 Load “Read Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 SII 0_0000_1100_00 Read Flash SDO x_xxxx_xxxx_xx Low and High SDI 0_0000_0000_00 Bytes SII 0_0111_1000_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0001_00 Load “ ...
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... Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Instr.1/5 SDI 0_0010_0000_00 Write Lock SII 0_0100_1100_00 Bits SDO x_xxxx_xxxx_xx SDI 0_0000_0100_00 Read Fuse SII 0_0100_1100_00 Low Bits SDO x_xxxx_xxxx_xx SDI 0_0000_0100_00 Read Fuse SII 0_0100_1100_00 High Bits SDO x_xxxx_xxxx_xx SDI ...
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... Output Low Voltage V (6) OL Except RESET pin (5) Output High-voltage V (6) OH Except RESET pin Input Leakage I LIL Current I/O Pin Input Leakage I LIH Current I/O Pin R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor PU ATtiny24/44/84 174 *NOTICE: +0. -40°C to +85°C A Condition Min V = 1.8 - 2. 2 1.8 - 2.4V 0. 2.4 - 5.5V 0.6V CC ...
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... 5V 3V) under steady state CC CC exceeds the test condition Figure 21-24, Figure 21-25, Figure 21-26, and 35. Power Reduction is As shown in CC. relationship is linear between 1.8V < (ATtiny24V/44V/84V) CC Safe Operating Area 2.7V Units µA µ Figure 21-27 Figure 20-1 and < 2. ...
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... Safe Operating Area 2. Fixed voltage within: (2) 1.8 – 5.5V (3) 2.7 – 5.5V 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). 2. Voltage range for ATtiny24V/44V/84V. 3. Voltage range for ATtiny24/44/84. (ATtiny24/44/84) 4.5V 5.5V Figure 21-40 on page 206 and Accuracy at given voltage Temperature & temperature 25°C Fixed temperature within: -40° ...
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... RESET Pin Threshold Voltage Minimum pulse width on RESET Pin Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset Internal bandgap reference voltage Internal bandgap reference start-up time Internal bandgap reference current consumption 1. Values are guidelines only. ATtiny24/44/ 2 4 Max. Min. Max. Min ...
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... Two versions of power-on reset have been implemented, as follows. 20.5.1 Standard Power-On Reset This implementation of power-on reset existed in early versions of ATtiny24/44/84. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: • ATtiny24, revision D, and older • ...
Page 179
... C to +85 A Condition 1.8 - 5.5V CC ATtiny24/44/84 (1) (1) Min Typ Max BOD Disabled 1.7 1.8 2.0 2.5 2.7 2.9 4.1 4.3 4.5 Reserved = V during the production test. This guar- CC BOT drops to a voltage where correct CC ° C Min Typ / 2 < ...
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... A External Voltage Reference REF V Internal Voltage Reference INT R Reference Input Resistance REF R Analog Input Resistance AIN ADC Conversion Output Note: 1. Values are guidelines only. ATtiny24/44/84 180 Condition Min 4V, REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 1 MHz ...
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... ADC clock = 50 - 200 kHz Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200 kHz Gain = 20x REF CC ADC clock = 50 - 200 kHz Free Running Conversion 70 50 GND 2.0 1.0 0 ATtiny24/44/84 (1) (1) Typ Max Units 10 Bits 10 Bits 10.0 LSB 20.0 LSB 4.0 LSB 10.0 LSB 10.0 LSB 15.0 LSB 3.0 LSB 4 ...
Page 182
... A External Reference Voltage REF V Internal Voltage Reference INT R Reference Input Resistance REF R Analog Input Resistance AIN ADC Conversion Output Note: 1. Values are guidelines only. ATtiny24/44/84 182 = -40°C to +85°C A (1) Condition Min Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200 kHz ...
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... SAMPLE (Unless Otherwise Noted) Parameter Oscillator Frequency (ATtiny24/44/84V) Oscillator Period (ATtiny24/44/84V) Oscillator Freq. (ATtiny24/44/84, V Oscillator Period (ATtiny24/44/84, V SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High for f < 12 MHz ...
Page 184
... Table 20-13. High-voltage Serial Programming Characteristics Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB ATtiny24/44/84 184 t IVSH SCI (PB0) SDO (PA4 25° (Unless otherwise noted Parameter SCI (PB0) Pulse Width High SCI (PB0) Pulse Width Low SDI (PA6), SII (PB1) Valid to SCI (PB0) High ...
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... Additional Current Consumption for the different I/O modules (absolute values 2V 1MHz CC 5.1 µA 6.6 µA 3.7 µA 29.6 µA below can be used for calculating typical current consumption for other supply volt- ATtiny24/44/84 = average switching frequency of SW “Power Reduction Register” on page 35 Typical numbers 4MHz 8MHz ...
Page 186
... USI, TIMER0, and ADC enabled is therefore: ≈ I CCTOT 21.2 Active Supply Current Figure 21-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ATtiny24/44/84 186 Additional Current Consumption (percentage) in Active and Idle mode Current consumption additional to active mode with external clock (see Figure 21-1 ...
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... ACTIVE SUPPLY CURRENT vs. FREQUENCY Frequency (MHz) (Internal RC Oscillator, 8 MHz) CC ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL RC OSCILLATOR, 8 MHz 1.5 2 2 ATtiny24/44/84 (PRR=0xFF °C 85 °C -40 °C 4 4.5 5 5.5 (V) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 187 ...
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... Figure 21-4. Active Supply Current vs. V Figure 21-5. Active Supply Current vs. V ATtiny24/44/84 188 (Internal RC Oscillator, 1 MHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 V (V) CC (Internal RC Oscillator, 128 kHz) CC ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 KHz 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2 °C 25 ° ...
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... Figure 21-7. Idle Supply Current vs. Frequency ( MHz) 8006K–AVR–10/10 IDLE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0. 0.1 0.2 0.3 0.4 Frequency (MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 1 Frequency (MHz) ATtiny24/44/84 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0.5 0.6 0.7 0.8 0.9 1 5.5 V 5.0 V 4.5 V 4.0 V 3 189 ...
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... Figure 21-8. Idle Supply Current vs. V Figure 21-9. Idle Supply Current vs. V ATtiny24/44/84 190 (Internal RC Oscillator, 8 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 VCC (V) (Internal RC Oscillator, 1 MHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 1 3.5 4 4 °C 25 °C -40 ° ...
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... RC Oscillator, 128 kHz) CC IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 128 KHz 0.03 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 ATtiny24/44/84 CC 3.5 4 4.5 5 5.5 V (V) CC (Watchdog Timer Disabled 3.5 4 4.5 5 5.5 V (V) CC -40 °C 25 °C 85 °C 85 °C 25 °C -40 °C 191 ...
Page 192
... Figure 21-12. Power-down Supply Current vs. V 21.5 Standby Supply Current Figure 21-13. Standby Supply Current vs. V ATtiny24/44/84 192 POWER-DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 1 Disabled) STANDBY SUPPLY CURRENT vs MHz EXTERNAL CRYSTAL, WATCHDOG TIMER DISABLED 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 ...
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... I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 0.2 0.4 0.6 0.8 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 0.5 1 ATtiny24/44/84 = 1.8V 1.8V 1 1.2 1.4 1.6 1 2.7V 2.7V 1.5 2 2 ˚C 85 ˚C -40 ˚ ˚C 85 ˚C -40 ˚C 3 193 ...
Page 194
... Figure 21-16. I/O pin Pull-up Resistor Current vs. Input Voltage (V Figure 21-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V ATtiny24/44/84 194 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE V 160 140 120 100 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE ...
Page 195
... Figure 21-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V 8006K–AVR–10/10 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 0.5 1 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 120 100 ATtiny24/44/84 = 2.7V 2.7V CC 1.5 2 2.5 V (V) RESET = 5V (V) RESET 25 ˚C -40 ˚C 85 ˚ ˚ ...
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... Pin Driver Strength Figure 21-20. I/O Pin Output Voltage vs. Sink Current (V Figure 21-21. I/O pin Output Voltage vs. Sink Current (V ATtiny24/44/84 196 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT V 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT V 0.7 0.6 0.5 0.4 0.3 0 ˚C 25 ˚C -40 ˚ ...
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... Figure 21-23. I/O Pin output Voltage vs. Source Current (V 8006K–AVR–10/10 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT V 3.5 3 2.5 2 1 I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 5.1 5 4.9 4.8 4.7 4.6 4.5 4.4 4 ATtiny24/44/ -40 ˚C 25 ˚C 85 ˚ (mA 5V -40 ˚C 25 ˚C 85 ˚ (mA 197 ...
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... Figure 21-24. Reset Pin Output Voltage vs. Sink Current (V Figure 21-25. Reset Pin Output Voltage vs. Sink Current (V ATtiny24/44/84 198 RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT V CC 1 0.5 1 1.5 I (mA) OL RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT 0.8 0.6 0.4 0 0.5 1 1.5 I (mA 3V °C 0 °C -45 ° ...
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... Figure 21-27. Reset Pin Output Voltage vs. Source Current (V 8006K–AVR–10/10 RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 3.5 3 2.5 2 1 RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT 5 4.5 4 3.5 3 2 ATtiny24/44/ 1.5 2 (mA 1.5 2 (mA) -45 °C 25 °C 85 °C -45 °C 25 °C 85 °C 199 ...
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... Pin Threshold and Hysteresis Figure 21-28. I/O Pin Input Threshold Voltage vs. V Figure 21-29. I/O Pin Input threshold Voltage vs. V ATtiny24/44/84 200 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIH, IO PIN READ AS '1' 3.5 3 2.5 2 1.5 1 0.5 0 1 I/O PIN INPUT THRESHOLD VOLTAGE vs. V VIL, IO PIN READ AS '0' 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 ...