ATtiny24 Atmel Corporation, ATtiny24 Datasheet - Page 4

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ATtiny24

Manufacturer Part Number
ATtiny24
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny24

Flash (kbytes)
2 Kbytes
Pin Count
14
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
12
Ext Interrupts
12
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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2. Overview
4
ATtiny24/44/84
ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
Figure 2-1.
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
GND
VCC
Block Diagram
PROGRAMMING
INSTRUCTION
PROGRAM
PROGRAM
REGISTER
INSTRUCTION
COUNTER
CONTROL
DECODER
FLASH
LINES
LOGIC
DATA REGISTER
PORT A
PORT A DRIVERS
ISP INTERFACE
PA7-PA0
REGISTERS
POINTER
REGISTER
PURPOSE
GENERAL
STATUS
STACK
SRAM
ALU
X
Y
Z
REG.PORT A
DATA DIR.
8-BIT DATABUS
ADC
MCU CONTROL
MCU STATUS
OSCILLATOR
WATCHDOG
INTERRUPT
REGISTER
REGISTER
INTERNAL
COUNTER0
COUNTER1
EEPROM
TIMER/
TIMER/
DATA REGISTER
TIMER
UNIT
PORT B
PORT B DRIVERS
PB3-PB0
OSCILLATORS
CALIBRATED
OSCILLATOR
TIMING AND
REG.PORT B
INTERNAL
CONTROL
DATA DIR.
8006KS–AVR–10/10

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