ATtiny24 Automotive Atmel Corporation, ATtiny24 Automotive Datasheet - Page 104

• Manufacturer Part Number: ATtiny24 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny24 Automotive

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.9.3
104
Atmel ATtiny24/44/84 [Preliminary]
Fast PWM Mode
The timing diagram for the CTC mode is shown in
(TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then coun-
ter (TCNT1) is cleared.
Figure 14-6. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the top value by either
using the OCF1A or ICF1 flag according to the register used to define the top value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the top value. How-
ever, changing the top to a value close to bottom when the counter is running with no or a low
prescaler value must be done with care because the CTC mode does not have the double
buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of
TCNT1, the counter will miss the compare match. The counter will then have to count to its
maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can
occur. In many cases this feature is not desirable. An alternative will then be to use the fast
PWM mode, using OCR1A for defining top (WGM13:0 = 15) because OCR1A then will be dou-
ble buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its log-
ical level on each compare match by setting the compare output mode bits to toggle mode
(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction
for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum
frequency of
defined by the following equation:
The variable N represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV1 flag is set on the same timer clock cycle on
which the counter counts from max to 0x0000.
The fast pulse width modulation, or fast PWM, mode (WGM13:0 = 5, 6, 7, 14, or 15) provides
a high-frequency PWM waveform generation option. The fast PWM differs from the other
PWM options by its single-slope operation. The counter counts from bottom to top then
restarts from bottom.
f
OCnA
TCNTn
OCnA
(Toggle)
Period
=
------------------------------------------------------- -
2
1
N
A
= f
f
clk_I/O
1
clk_I/O
+
1
OCRnA
/2 when OCR1A is set to zero (0x0000). The waveform frequency is
2
3
Figure 14-6 on page
4
104. The counter value
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnA1:0 = 1)
7701E–AVR–02/11