ATtiny24 Automotive Atmel Corporation, ATtiny24 Automotive Datasheet - Page 44

• Manufacturer Part Number: ATtiny24 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny24 Automotive

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

9.7
9.7.1
9.8
44
Internal Voltage Reference
Watchdog Timer
Atmel ATtiny24/44/84 [Preliminary]
Voltage Reference Enable Signals and Start-up Time
Figure 9-6.
The Atmel
Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
the reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the
three conditions above to ensure that the reference is turned off before entering Power-down
mode.
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128kHz. By control-
ling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
Table 9-4 on page
The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten dif-
ferent clock cycle periods can be selected to determine the reset period. If the reset period
expires without another Watchdog Reset, the Atmel ATtiny24/44/84 resets and executes from
the Reset Vector. For timing details on the Watchdog Reset, refer to
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This
can be very helpful when using the Watchdog to wake-up from Power-down.
ACBG bit in ACSR).
CC
®
ATtiny24/44/84 features an internal bandgap reference. This reference is used for
Watchdog Reset During Operation
48. The WDR – Watchdog Reset – instruction resets the Watchdog Timer.
“System and Reset Characterizations” on page
CK
Table 9-4 on page
181. To save power,
7701E–AVR–02/11
48.