ATtiny24 Automotive Atmel Corporation, ATtiny24 Automotive Datasheet - Page 45

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ATtiny24 Automotive

Manufacturer Part Number
ATtiny24 Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATtiny24 Automotive

Flash (kbytes)
2 Kbytes
Pin Count
14
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
4
Hardware Qtouch Acquisition
No
Max I/o Pins
12
Ext Interrupts
12
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.12
Eeprom (bytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
9.9
9.9.1
9.9.2
7701E–AVR–02/11
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 1
Safety Level 2
To prevent unintentional disabling of the watchdog or unintentional change of time-out period,
two different safety levels are selected by the WDTON fuse, as shown in Table 9-2. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45
details.
Table 9-2.
Figure 9-7.
The sequence for changing configuration differs slightly between the two safety levels. Sepa-
rate procedures are described for each level.
In this mode, the watchdog timer is initially disabled, but can be enabled by writing the WDE
bit to logical one without any restriction. A timed sequence is needed when disabling an
enabled watchdog timer. To disable an enabled watchdog timer, the following procedure must
be followed:
1. In the same operation, write a logical one to WDCE and WDE. A logical one must be
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits
In this mode, the watchdog timer is always enabled, and the WDE bit will always read as logi-
cal one. A timed sequence is needed when changing the watchdog time-out period. To
change the watchdog time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
WDTON
Unprogrammed
Programmed
written to WDE regardless of the previous value of the WDE bit.
as desired, but with the WDCE bit cleared.
always is set, the WDE must be written to one to start the timed sequence.
but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
WDT Configuration as a Function of the Fuse Settings of WDTON
Watchdog Timer
Safety
Level
1
2
WATCHDOG
OSCILLATOR
Atmel ATtiny24/44/84 [Preliminary]
RESET
128 kHz
WDP0
WDP1
WDP2
WDP3
WDE
WDT Initial
State
Disabled
Enabled
How to Disable the
WDT
Timed sequence
Always enabled
MCU RESET
PRESCALER
WATCHDOG
How to Change
Time-out
No limitations
Timed sequence
for
45

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