ATtiny24 Automotive Atmel Corporation, ATtiny24 Automotive Datasheet - Page 80

• Manufacturer Part Number: ATtiny24 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATtiny24 Automotive

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

The extreme values for the OCR0A register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to bottom, the out- put will
be a narrow spike for each max+1 timer clock cycle. Setting the OCR0A equal to max will
result in a constantly high or low output (depending on the polarity of the output set by the
COM0A1:0 bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The wave-
form generated will have a maximum frequency of
= f
/2 when OCR0A is set to zero.
0
clk_I/O
This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the
output compare unit is enabled in the fast PWM mode.
13.7.4
Phase Correct PWM Mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from bottom to top and then from top to bottom. Top
is defined as 0xFF when WGM2:0 = 1, and as OCR0A when WGM2:0 = 5. In non-inverting
compare output mode, the output compare (OC0x) is cleared on the compare match between
TCNT0 and OCR0x while up-counting, and set on the compare match while down-counting. In
inverting output compare mode, the operation is inverted. The dual-slope operation has lower
maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode
is shown on
Figure 13-7 on page
81. The TCNT0 value is in the timing diagram, which is
shown as a histogram for illustrating the dual-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal lines on the TCNT0 slopes rep-
resent compare matches between OCR0x and TCNT0.
Atmel ATtiny24/44/84 [Preliminary]
80
7701E–AVR–02/11