ATtiny24A Atmel Corporation, ATtiny24A Datasheet
ATtiny24A
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... Low Power Consumption – Active Mode: • 210 µA at 1.8V and 1 MHz – Idle Mode: • 33 µA at 1.8V and 1 MHz – Power-down Mode: • 0.1 µA at 1.8V and 25°C ® 8-bit Microcontroller 8-bit Microcontroller with 2K/4K/8K Bytes In-System Programmable Flash ATtiny24A * ATtiny44A ATtiny84A * * Preliminary Rev. 8183D–AVR–04/11 ...
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... PA7 6 7 QFN/MLF/VQFN 1 (ADC3/T0/PCINT3) PA3 2 (ADC2/AIN1/PCINT2) PA2 3 (ADC1/AIN0/PCINT1) PA1 4 (ADC0/AREF/PCINT0) PA0 5 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect UFBGA - Pinout ATtiny24A/44A/84A (top view PA5 PA4 PA7 PA3 PA2 PA0 GND 14 GND 13 PA0 (ADC0/AREF/PCINT0) 12 PA1 (ADC1/AIN0/PCINT1) 11 PA2 (ADC2/AIN1/PCINT2) ...
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... RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny24A/44A/84A as listed in Section 10.2 “Alternate Port Functions” on page 1 ...
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... Overview ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. VCC GND The AVR core combines a rich instruction set with 32 general purpose working registers ...
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... ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface conventional non-volatile memory programmer on-chip boot code running on the AVR core. The ATtiny24A/44A/84A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits. ...
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... PPM over 20 years at 85°C or 100 years at 25°C. 3.5 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized. ATtiny24A/44A/84A 6 ® ® and QMatrix acquisi- ...
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... The Program memory is In-System Reprogrammable Flash memory. 8183D–AVR–04/11 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATtiny24A/44A/84A Data Bus 8-bit Status and Control Interrupt Unit General Purpose Watchdog Registrers Timer ADC ...
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... This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. ATtiny24A/44A/84A 8 8183D–AVR–04/11 ...
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... Registers R17 … R26 R27 R28 R29 R30 R31 Figure 4-2, each register is also assigned a Data memory address, mapping them The X-, Y-, and Z-registers 15 XH ATtiny24A/44A/84A 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... No internal clock division is used. Figure 4-4 vard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. ATtiny24A/44A/84A 10 7 R27 (0x1B) 15 ...
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... The Parallel Instruction Fetches and Instruction Executions T1 clk CPU shows the internal timing concept for the Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Result Write Back ATtiny24A/44A/84A “Interrupts” on page 47. The list also ...
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... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ Note: ATtiny24A/44A/84A 12 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) See “ ...
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... Global Interrupt Enable See “Code Examples” on page SP15 SP14 SP13 SP7 SP6 SP5 R/W R/W R/W R/W R/W R/W RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND ATtiny24A/44A/84A SP12 SP11 SP10 SP9 SP4 SP3 SP2 SP1 R/W R/W R/W R/W R/W R/W R/W R/W RAMEND RAMEND RAMEND RAMEND ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATtiny24A/44A/84A ...
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... Memories This section describes the different memories in the ATtiny24A/44A/84A. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny24A/44A/84A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
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... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data SRAM in the ATtiny24A/44A/84A are all accessible through all these addressing modes. The Register File is described in Figure 5-2. ...
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... Table 5-1 on page 22. The EEPE bit remains set until the erase and write opera- Table 5-1 on page 22). The EEPE bit remains set until the erase operation ATtiny24A/44A/84A Table 5-1 on page 22. A self-timing func- for details on how to avoid “Split Byte Programming” on page 17 Table 5-1 on page 22) ...
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... Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } Note: ATtiny24A/44A/84A 18 r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 ; See “Code Examples” on page 6. “OSCCAL – Oscillator Calibration Register” on 8183D–AVR–04/11 ...
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... Set up address register */ EEAR = ucAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; See “Code Examples” on page 6. , the EEPROM data can be corrupted because the supply voltage is CC ATtiny24A/44A/84A reset protection circuit can CC 19 ...
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... I/O Memory The I/O space definition of the ATtiny24A/44A/84A is shown in 266. All ATtiny24A/44A/84A I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny44A. In devices with less EEPROM, i.e. ATtiny24A, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed. • ...
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... If a write operation is in progress neither possible to read the EEPROM, nor to change the EEAR Register. 5.5.5 GPIOR2 – General Purpose I/O Register 2 Bit 0x15 (0x35) Read/Write Initial Value ATtiny24A/44A/84A 22 EEPROM Programming Mode Bits and Programming Times EEPM0 Programming Time Operation 0 3.4 ms ...
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... Read/Write Initial Value 5.5.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x13 (0x33) Read/Write Initial Value 8183D–AVR–04/ MSB R/W R/W R/W R MSB R/W R/W R/W R ATtiny24A/44A/84A LSB R/W R/W R/W R LSB R/W R/W R/W R GPIOR1 GPIOR0 23 ...
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... Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. ATtiny24A/44A/84A 24 presents the principal clock systems in the AVR and their distribution. All of the clocks 33 ...
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... Device Clocking Options page 26) page page 27) page 28) page 1. For all fuses “1” means unprogrammed and “0” means programmed. Number of Watchdog Oscillator Cycles Typ Time-out ATtiny24A/44A/84A CKSEL[3:0] 26) 28) Table Number of Cycles 512 8K (8,192) (1) 0000 0001 0010 0011 0100 ...
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... OSCCAL Register and thereby automatically cal- ibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 20-2 on page ATtiny24A/44A/84A 26 26. To run the device on an external clock, the CKSEL Fuses must be programmed to External Clock Drive Configuration ...
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... Start-up Time from Power-down the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + ensure programming mode can be entered. ATtiny24A/44A/84A “OSCCAL – Oscillator Calibration Register” on Table 20-2 on page 161. Nominal Frequency 8.0 MHz Additional Delay from Reset ( ...
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... C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for ATtiny24A/44A/84A 28 Figure 6-3. To find suitable capacitors please consult the manufacturer’s datasheet. ...
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... These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. ATtiny24A/44A/84A below. For ceramic resonators, the capacitor values Recommended C1 and C2 Value (pF) – ...
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... MHz. 6.3 System Clock Prescaler The ATtiny24A/44A/84A system clock can be divided by setting the Register” on page requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk ...
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... CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A/84A and will always read as zero. 8183D–AVR–04/ ...
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... The device is shipped with the CKDIV8 Fuse programmed. Table 6-11. CLKPS3 ATtiny24A/44A/84A 32 32. Clock Prescaler Select CLKPS2 CLKPS1 ...
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... MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 24 ATtiny24A/44A/84A. The figure is helpful in selecting an appropriate sleep mode. shows the different sleep modes and their wake up sources. Table 7-1. Sleep Mode Idle ...
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... Stand-By, while writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active. Writing to the BODS bit is controlled by a timed sequence and an enable bit, see MCU Control Register” on page ATtiny24A/44A/84A 34 129. This will reduce power consumption in Idle level has dropped during the sleep period. ...
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... Current of I/O Modules” on page 182 “Analog to Digital Converter” on page 132 “Analog Comparator” on page 128 “Brown-out Detection” on page 40 for details on how to configure the Brown-out Detector. ATtiny24A/44A/84A 37, pro- for examples. In all for details on how to config- and “Software BOD Dis- ...
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... To avoid the MCU entering the sleep mode unless it is the programmer’s purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. ATtiny24A/44A/84A 36 for details on the start-up time. ...
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... Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. • Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. ...
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... This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in ATtiny24A/44A/84A 38 Figure 8-1 shows the reset logic. Electrical parameters of the Table 20-4 on page 176 ...
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... Reset Sources The ATtiny24A/44A/84A has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled • ...
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... Figure 8-4. 8.2.3 Brown-out Detection ATtiny24A/44A/84A has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Timer” on page 41 Figure 8-6. 8.3 Internal Voltage Reference ATtiny24A/44A/84A features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or the ADC. The band- gap voltage varies with supply voltage and temperature. 8.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...
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... Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed the same operation, write a logic one to WDCE and WDE. A logic one must be b. Within the next four clock cycles, in the same operation, write the WDE and WDP ATtiny24A/44A/84A 42 WDT Configuration as a Function of the Fuse Settings of WDTON Safety ...
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... WDTCSR, r16 ; Turn off WDT ldi r16, (0<<WDE) out WDTCSR, r16 ret _WDR(); /* Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; See “Code Examples” on page 6. ATtiny24A/44A/84A 43 ...
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... Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
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... To avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the initialization routine. ATtiny24A/44A/84A Action on Time-out None ...
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... The different prescaling values and their corresponding Timeout Periods are shown in Table 8-3. Table 8-3. WDP3 Note: ATtiny24A/44A/84A 46 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 ...
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... In case the program never enables an interrupt source, the Interrupt Vectors will not be used and, consequently, regular program code can be placed at these locations. The most typical and general setup for interrupt vector addresses in ATtiny24A/44A/84A is shown in the program example below. 8183D–AVR–04/11 11 ...
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... Low Level Interrupt A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle). ATtiny24A/44A/84A 48 rjmp RESET rjmp INT0 ...
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... Pin Change Interrupt Timing A timing example of a pin change interrupt is shown in Figure 9-1. PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 8183D–AVR–04/11 24. Timing of pin change interrupts pin_lat pcint_in_( pin_sync LE clk PCINT(0) in PCMSK(x) clk ATtiny24A/44A/84A Figure 9-1. 0 pcint_syn pcint_setflag PCIF x clk 49 ...
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... Initial Value • Bits 7, 3:0 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...
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... Read/Write Initial Value • Bits 7, 3:0 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor- responding Interrupt Vector ...
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... Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0 Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny24A/44A/84A ...
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... Ground as indicated in CC for a complete list of parameters. I/O Pin Equivalent Schematic Pxn C pin “Register Description” on page 58. Refer to the individual module sections for a full description of the alter- ATtiny24A/44A/84A Figure 10-1 on page 53. See “Electri Logic See Figure "General Digital I/O" for Details 66. “ ...
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... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATtiny24A/44A/84A 54 (1) General Digital I/O ...
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... X Output 1 X Output Figure 10-2 on page Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATtiny24A/44A/84A Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) 54, the PINxn Register bit and the preced- and t respectively ...
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... Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is ATtiny24A/44A/84A 56 Figure 10-4 on page 56. The out instruction sets the “SYNC LATCH” signal at the ...
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... Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTA = (1<<PA4)|(1<<PA1)|(1<<PA0); DDRA = (1<<DDA3)|(1<<DDA2)|(1<<DDA1)|(1<<DDA0); /* Insert nop for synchronization*/ _NOP(); /* Read port pins */ i = PINA; ... See “Code Examples” on page 6. ATtiny24A/44A/84A 57 ...
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... DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: The illustration in the figure above serves as a generic description applicable to all port pins in the AVR microcontroller family. Some overriding signals may not be present in all port pins. ATtiny24A/44A/84A 58 (1) Alternate Port Functions PUOExn PUOVxn ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/Output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATtiny24A/44A/84A Fig- 59 ...
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... AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer Selection Register (ADMUX). • PCINT0: Pin Change Interrupt source 0. The PA0 pin can serve as an external interrupt source for pin change interrupt 0. ATtiny24A/44A/84A 60 Port A Pins Alternate Functions Port Pin ...
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... The OC1B pin is also the output pin for the PWM mode timer function. • PCINT5: Pin Change Interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change interrupt 0. 8183D–AVR–04/11 ATtiny24A/44A/84A . . . . ...
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... Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny24A/44A/84A 62 Table 10-5 and Table 10-6 relate the alternate functions of Port A to the overriding Figure 10-5 on page 58. Overriding Signals for Alternate Functions in PA[7:5] PA7/ADC7/OC0B/ICP1/ PA6/ADC6/DI/SDA/MOSI/ PCINT7 OC1A/ PCINT6 ...
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... ADC3 Input Overriding Signals for Alternate Functions in PA[1:0] PA1/ADC1/AIN0/PCINT1 PCINT1 • PCIE0 + ADC1D PCINT1 • PCIE0 PCINT1 Input ADC1/Analog Comparator Positive Input ATtiny24A/44A/84A PA2/ADC2/AIN1/PCINT2 PCINT2 • PCIE + ADC2D PCINT2 • PCIE0 PCINT2 Input ADC2/Analog Comparator Negative Input PA0/ADC0/AREF/PCINT0 RESET • ...
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... CKOUT Fuse is programmed, regardless of the PORTB2 and DDB2 settings. It will also be output during reset. • PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt source for pin change interrupt 1. ATtiny24A/44A/84A 64 Port B Pins Alternate Functions Port Pin ...
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... PCINT11 • PCIE1 (2) DEBUGWIRE_ENABLE + (RSTDISBL PCINT11 • PCIE1) dW/PCINT11 Input RSTDISBL is 1 when the Fuse is “0” (Programmed). DebugWIRE is enabled when DWEN Fuse is programmed and Lock bits are unprogrammed. ATtiny24A/44A/84A relate the alternate functions of Port B to the 58. PB2/INT0/OC0A/CKOUT/PCINT10 (2) CKOUT 0 (2) CKOUT ...
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... PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See figuring the Pin” on page 54 10.3.2 PORTA – Port A Data Register Bit 0x1B (0x3B) Read/Write Initial Value 10.3.3 DDRA – Port A Data Direction Register Bit 0x1A (0x3A) Read/Write Initial Value ATtiny24A/44A/84A 66 Overriding Signals for Alternate Functions in PB[1:0] PB1/XTAL2/PCINT9 (1) EXT_OSC 0 (1) EXT_OSC 0 (1) EXT_OSC 0 0 ...
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... – – – – – – – – ATtiny24A/44A/84A PINA3 PINA2 PINA1 PINA0 R/W R/W R/W R/W N/A N/A N/A N PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 ...
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... A simplified block diagram of the 8-bit Timer/Counter is shown in the actual placement of I/O pins, refer to including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the Figure 11-1. ATtiny24A/44A/84A 68 Figure 1-1 on page “Register Description” on page 8-bit Timer/Counter Block Diagram ...
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... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment depends on the mode of operation “Timer/Counter Prescaler” on page shows a block diagram of the counter and its surroundings. ATtiny24A/44A/84A Figure 11-1) signals are all visible in the for details. The Compare Match event will also 113 ...
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... WGM0[2:0] bits and Compare Output mode (COM0x[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation. See Figure 11-3 on page 71 ATtiny24A/44A/84A 70 Counter Unit Block Diagram DATA BUS ...
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... OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. 8183D–AVR–04/11 Output Compare Unit, Block Diagram DATA BUS OCRnx = (8-bit Comparator ) m Waveform Generator ATtiny24A/44A/84A TCNTn OCFnx (Int.Req.) OCnx 71 ...
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... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x[1:0] bit settings are reserved for certain modes of operation, see ATtiny24A/44A/84A 72 Compare Match Output Unit, Schematic Waveform ...
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... Table 11-2 on page 79, and for phase correct PWM refer to “Modes of Operation” on page Figure 11-8 on page and Figure 11-11 on page 78 in “Timer/Counter Timing Diagrams” on page Figure 11-5 on page ATtiny24A/44A/84A 79. For fast PWM mode, refer to Table 11-4 on page 80. 73). 77, Figure 11-9 on page 78, Figure 74. The counter value ...
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... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast ATtiny24A/44A/84A 74 CTC Mode, Timing Diagram ...
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... The TCNT0 value is in the timing diagram Fast PWM Mode, Timing Diagram Table 11-3 on page f = OCnxPWM clk_I/O ATtiny24A/44A/84A OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx[1: (COMnx[1: 79). The actual OC0x value will only be vis- f clk_I/O ----------------- - ⋅ ...
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... In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x[1:0] bits to two will produce a non-inverted PWM. An inverted ATtiny24A/44A/84A 76 76. The TCNT0 value is in the timing diagram shown as a histogram for Phase Correct PWM Mode, Timing Diagram ...
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... Figure 11-7 on page 76 Figure 11-7 on page Figure 11-8 on page 77 contains timing data for basic Timer/Counter operation. Timer/Counter Timing Diagram, no Prescaling MAX - 1 MAX shows the same timing data, but with the prescaler enabled. ATtiny24A/44A/84A 80). The actual OC0x value will only be f clk_I/O = ----------------- - ⋅ N 510 OCn has a transition from high to low 76 ...
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... I/O clk Tn (clk /8) I/O TCNTn (CTC) OCRnx OCFnx ATtiny24A/44A/84A 78 Timer/Counter Timing Diagram, with Prescaler (f MAX - 1 MAX shows the setting of OCF0B in all modes and OCF0A in all modes OCRnx - 1 OCRnx OCRnx Value shows the setting of OCF0A and the clearing of TCNT0 in CTC mode Prescaler (f /8) ...
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... Set OC0A on Compare Match 1 Clear OC0A at BOTTOM (inverting mode special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 74 for more details. ATtiny24A/44A/84A COM0B0 – ...
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... Table 11-6 Table 11-6. COM0B1 Note: ATtiny24A/44A/84A 80 shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to phase Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. 1 WGM02 = 1: Toggle OC0A on Compare Match. ...
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... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. • Bits 1:0 – WGM0[1:0]: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- ...
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... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS0[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 83
... TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit 0x39 (0x59) Read/Write Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero. 8183D–AVR–04/11 Clock Select Bit Description (Continued) CS01 CS00 Description ...
Page 84
... Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero. • Bit 2 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...
Page 85
... I/O pins, refer to I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 12-1. 8183D–AVR–04/11 “Pinout of ATtiny24A/44A/84A” on page “Register Description” on page 16-bit Timer/Counter Block Diagram Count Clear Control Logic ...
Page 86
... The following definitions are used extensively throughout the section: Table 12-1. Constant BOTTOM MAX TOP ATtiny24A/44A/84A 86 90. The compare match event will also set the Compare Match 128). The Input Capture unit includes a digital filtering unit (Noise Definitions Description The counter reaches BOTTOM when it becomes 0x00 ...
Page 87
... Prescaler” on page shows a block diagram of the counter and its surroundings. Counter Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) Count TCNTnL (8-bit) Clear Direction TCNTn (16-bit Counter) ATtiny24A/44A/84A 113. TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) ...
Page 88
... The Input Capture unit is illustrated by the block diagram shown in elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. ATtiny24A/44A/84A 88 Figure Increment or decrement TCNT1 by 1. ...
Page 89
... Input Capture Unit Block Diagram DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) ACO* ACIC* Analog Comparator 103. ATtiny24A/44A/84A (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge Canceler Detector “Accessing 16-bit Registers” ...
Page 90
... I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM1[3:0]) bits and Compare Output mode (COM1x[1:0]) bits. The TOP and BOTTOM signals ATtiny24A/44A/84A 90 (Figure 13-1 on page 113). The edge detector is also ...
Page 91
... DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) = TOP Waveform Generator BOTTOM WGMn[3:0] ATtiny24A/44A/84A 94). (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) (16-bit Comparator ) OCFnx (Int.Req.) COMnx[1:0] OCnx 91 ...
Page 92
... PORT) that are affected by the COM1x[1:0] bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin system reset occur, the OC1x Register is reset to “0”. ATtiny24A/44A/84A 92 103. ...
Page 93
... PORT D Q DDR Table 12-2 on page for details. “Register Description” on page 106 Table 12-2 on page 107, and for phase correct and phase and frequency correct PWM refer to 107. ATtiny24A/44A/84A 1 OCnx Pin 0 107, Table 12-3 on page 107 107. For fast PWM mode refer to 93 ...
Page 94
... The timing diagram for the CTC mode is shown in (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. ATtiny24A/44A/84A 94 (“Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page ...
Page 95
... PWM mode well suited for power regulation, rectification, and DAC 8183D–AVR–04/11 CTC Mode, Timing Diagram when OCR1A is set to zero (0x0000). The waveform frequency is defined by clk_I --------------------------------------------------- ⋅ OCnA 2 N ATtiny24A/44A/84A OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA[1: clk_I/O ⋅ OCRnA ...
Page 96
... The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ATtiny24A/44A/84A 96 R ...
Page 97
... In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. 8183D–AVR–04/11 ATtiny24A/44A/84A Table 12-3 on page f clk_I/O f ...
Page 98
... Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in changing the TOP actively while the Timer/Counter is running in the phase correct mode can ATtiny24A/44A/84A 98 ( log ...
Page 99
... The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and 8183D–AVR–04/11 f OCnxPCPWM and Figure 12-9 on page 100). ATtiny24A/44A/84A Table 12-4 on page f clk_I/O = --------------------------- - ⋅ ⋅ TOP ...
Page 100
... Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 12-9 on page 100 mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. ATtiny24A/44A/84A 100 log R = ---------------------------------- - ...
Page 101
... The actual OC1x value will only be visible on the port pin if the data direction f OCnxPFCPWM Figure 12-10 shows a timing diagram for the setting of OCF1x. OCRnx - 1 OCRnx OCRnx Value shows the same timing data, but with the prescaler enabled. ATtiny24A/44A/84A f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown as a ...
Page 102
... TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICFn as TOP) OCRnx (Update at TOP) Figure 12-13 on page 103 ATtiny24A/44A/84A 102 OCRnx - 1 OCRnx shows the count sequence close to TOP in various modes. When using phase and I/O Tn /1) I/O TOP - 1 TOP - 1 (FPWM) (if used Old OCRnx Value shows the same timing data, but with the prescaler enabled ...
Page 103
... OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. 8183D–AVR–04/11 clk I/O clk Tn /8) I/O TOP - 1 TOP - 1 (FPWM) (if used Old OCRnx Value ATtiny24A/44A/84A /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value TOP - 2 103 ...
Page 104
... Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret ATtiny24A/44A/84A 104 See “Code Examples” on page 6. 8183D–AVR–04/11 ...
Page 105
... Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; See “Code Examples” on page 6. ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret ATtiny24A/44A/84A 105 ...
Page 106
... I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond- ing to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x[1:0] bits is depen- dent of the WGM1[3:0] bits setting. ATtiny24A/44A/84A 106 See “Code Examples” on page 6 ...
Page 107
... Set OC1A/OC1B on Compare Match when downcounting Set OC1A/OC1B on Compare Match when up-counting 1 1 Clear OC1A/OC1B on Compare Match when downcounting 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 97 ATtiny24A/44A/84A (1) for more details. “Fast (1) 107 ...
Page 108
... This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. ATtiny24A/44A/84A 108 Table 12-5 on page ...
Page 109
... TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Res: Reserved Bit This bit is reserved in the ATtiny24A/44A and will always read as zero. • Bits 4:3 – WGM1[3:2]: Waveform Generation Mode See TCCR1A Register description. ...
Page 110
... A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bits 5:0 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. 12.11.4 TCNT1H and TCNT1L – Timer/Counter1 Bit ...
Page 111
... Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “ ...
Page 112
... Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved bits in the ATtiny24A/44A/84A and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM1[3: used as the TOP value, the ICF1 flag is set when the coun- ter reaches the TOP value ...
Page 113
... Alternatively, one of four taps from the prescaler can be used CLK_I/O /1024. CLK_I/O pulse for each positive (CSn[2: negative Pin Sampling Synchronization ATtiny24A/44A/84A /8, f /64, CLK_I/O CLK_I/O ). The Tn Figure 13-1 on page 113 ). The latch is clk I/O Tn_sync D Q (To Clock ...
Page 114
... Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advanc- ATtiny24A/44A/84A 114 < f /2) given a 50/50% duty cycle ...
Page 115
... When the TSM bit is written to zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting. • Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. 8183D–AVR–04/11 ATtiny24A/44A/84A 115 ...
Page 116
... USI Data Register and the output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. ATtiny24A/44A/84A 116 “Pinout of ATtiny24A/44A/84A” on page “Register Descriptions” on page Universal Serial Interface, Block Diagram ...
Page 117
... Three-wire Mode Operation, Simplified Diagram Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MASTER shows two USI units operating in three-wire mode, one as Master and one as Slave. ATtiny24A/44A/84A DO DI USCK DO DI USCK PORTxn 117 ...
Page 118
... Depending on the protocol used the slave device can now set its output to high impedance. 14.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: <continues> ATtiny24A/44A/84A 118 Three-wire Mode, Timing Diagram ( Reference ) MSB ...
Page 119
... USICR,r16 ; MSB out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 ; LSB out USICR,r17 in r16,USIDR ATtiny24A/44A/84A 119 ...
Page 120
... This means that the master must always check if the SCL line was actually released after it has generated a positive edge. Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORTA register. ATtiny24A/44A/84A 120 ldi r16,(1<<USIWM0)|(1<<USICS1) out ...
Page 121
... Bit2 Bit1 Bit0 MASTER Two-wire Mode, Typical Timing Diagram ADDRESS R/W ACK (Figure 14-5), a bus transfer involves the following steps: ATtiny24A/44A/84A VCC SDA SCL HOLD SCL Two-wire Clock Control Unit SDA SCL PORTxn DATA ACK DATA ...
Page 122
... In two-wire slave mode the Two-wire Clock Con- trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the actual data rate in two-wire mode. ATtiny24A/44A/84A 122 Figure 14-6. The SDA line is delayed (in the range of 50 ...
Page 123
... The counter and USI 8183D–AVR–04/ USISIE USIOIE USIWM1 USIWM0 R/W R/W R/W R page 126 ATtiny24A/44A/84A USICS1 USICS0 USICLK USITC R/W R page 125 for further details. ...
Page 124
... USICLK bit clocks both the USI Data Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit. ATtiny24A/44A/84A 124 Relationship between USIWM[1:0] and USI Operation ...
Page 125
... External, negative edge USISIF USIOIF USIPF USIDC R/W R/W R ATtiny24A/44A/84A 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe (USITC) Table 14-2 USICNT3 USICNT2 ...
Page 126
... The shift operation can be synchronised to an external clock edge Timer/Counter0 Compare Match, or directly to software via the USICLK bit serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed. ATtiny24A/44A/84A 126 7 ...
Page 127
... USI flags as set similarly as when reading the USIDR register. The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has been completed. 8183D–AVR–04/ MSB ATtiny24A/44A/84A LSB USIBR 127 ...
Page 128
... If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX[1:0] in ADMUX select the input pin to replace the negative input to the analog comparator, as shown in ATtiny24A/44A/84A 128 15-1. Analog Comparator Block Diagram ...
Page 129
... Analog Comparator Negative Input X XXXXX AIN1 1 XXXXX AIN1 0 00000 ADC0 0 00001 ADC1 0 00010 ADC2 0 00011 ADC3 0 00100 ADC4 0 00101 ADC5 0 00110 ADC6 0 00111 ADC7 ACD ACBG ACO ACI R/W R N/A 0 ATtiny24A/44A/84A ACIE ACIC ACIS1 ACIS0 R/W R/W R/W R ACSR 129 ...
Page 130
... When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see ATtiny24A/44A/84A 130 Table 15-2. ...
Page 131
... ADC7D ADC6D ADC5D ADC4D R/W R/W R/W R ATtiny24A/44A/84A ADC3D ADC2D ADC1D ADC0D R/W R/W R/W R DIDR0 131 ...
Page 132
... Input Polarity Reversal Mode 16.2 Overview ATtiny24A/44A/84A features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). The ADC is wired to a nine-channel analog multiplexer, which allows the ADC to mea- sure the voltage at eight single-ended input pins, or between twelve differential pairs of input pins, or from one internal, single-ended voltage channel coming from the internal temperature sensor ...
Page 133
... ADC6 POS. ADC5 INPUT MUX ADC4 ADC3 ADC2 ADC1 ADC0 NEG. INPUT MUX for more details. ATtiny24A/44A/84A ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS 15 ADC CTRL. & STATUS A ADC DATA REGISTER REGISTER (ADCSRA) (ADCH/ADCL) TRIGGER SELECT PRESCALER CONVERSION LOGIC SAMPLE & HOLD ...
Page 134
... If another positive edge occurs on the trigger signal during con- version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus ATtiny24A/44A/84A 134 supply pin, the AREF pin and the internal 1.1V voltage reference. ...
Page 135
... MHz. Figure 16-3. 8183D–AVR–04/11 ADC Auto Trigger Logic ADTS[2:0] ADIF SOURCE EDGE DETECTOR SOURCE n ADSC ADC Prescaler ADEN START CK ADPS0 ADPS1 ADPS2 ATtiny24A/44A/84A PRESCALER START ADATE CONVERSION Reset 7-BIT ADC PRESCALER ADC CLOCK SOURCE CLK ADC LOGIC 135 ...
Page 136
... ADC clock edge. Figure 16-5. Cycle Number ADC Clock ADSC ADIF ADCH ADCL When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 16-6 ATtiny24A/44A/84A 136 ADC Timing Diagram, First Conversion (Single Conversion Mode) First Conversion ...
Page 137
... Hold Reset MUX and REFS Update Figure ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete ATtiny24A/44A/84A One Conversion Conversion Complete 16-7. Next Conversion Sign and MSB of Result LSB of Result Sample & ...
Page 138
... In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the ATtiny24A/44A/84A 138 Table 16-1 ...
Page 139
... S/H capacitor. 8183D–AVR–04/11 ) indicates the conversion range for the ADC. Single ended REF will result in codes close to 0x3FF. V REF ) through an internal amplifier. BG ATtiny24A/44A/84A can be selected as either REF Figure 16-8. An analog 139 ...
Page 140
... An n-bit single-ended ADC converts a voltage linearly between GND and V (LSBs). The lowest code is read as 0, and the highest code is read as 2 Several parameters describe the deviation from the ideal behavior, as follows: ATtiny24A/44A/84A 140 /2) should not be present. The user is advised to remove high fre- ...
Page 141
... Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. 8183D–AVR–04/11 Offset Error Output Code Offset Error Output Code Output Code ATtiny24A/44A/84A Ideal ADC Actual ADC V Input Voltage REF Gain Error Ideal ADC ...
Page 142
... If differential channels and an unipolar input mode are used, the result is where V and V REF than the voltage of the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) through 0x3FF (+1023d). The GAIN is either 1x or 20x. ATtiny24A/44A/84A 142 Output Code 0x3FF 1 LSB 0x000 0 ...
Page 143
... POS the selected voltage reference. The result is presented in two’s complement form, from Temperature vs. Sensor Output Voltage (Typical Case) ° -40 C 230 LSB Table 16-2 are typical values. However, due to process variation the ATtiny24A/44A/84A ) 512 ⋅ V – NEG ⋅ V REF the voltage on the negative input pin, NEG ° ...
Page 144
... ADCSRA is set). Special care should be taken when changing differential channels. Once a differential channel has been selected the input stage may take a while to stabilize therefore recommended to force the ADC to perform a long conversion when changing multiplexer settings. This can be ATtiny24A/44A/84A 144 7 6 ...
Page 145
... Table 16-5 on page 145 for details of selections of differential input channel selections as well as selec- Differential Input channel Selections. Negative Differential Input ADC0 (PA0) ADC1 (PA1) ADC3 (PA3) ADC0 (PA0) ADC2 (PA2) ADC3 (PA3) ATtiny24A/44A/84A MUX[5:0] 000000 000001 000010 000011 000100 000101 000110 000111 ...
Page 146
... Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. ATtiny24A/44A/84A 146 Differential Input channel Selections. (Continued) Negative Differential Input ...
Page 147
... These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 16-6. ADPS2 8183D–AVR–04/11 ADC Prescaler Selections ADPS1 ATtiny24A/44A/84A ADPS0 Division Factor 128 147 ...
Page 148
... Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result is represented in the two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. ATtiny24A/44A/84A 148 15 14 ...
Page 149
... Bit 3 – Res: Reserved Bit This bit is reserved bit in the ATtiny24A/44A/84A and will always read as what was wrote there. • Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion ...
Page 150
... Figure 17-1 connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. Figure 17-1. ATtiny24A/44A/84A 150 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator The debugWIRE Setup dW ...
Page 151
... This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. 8183D–AVR–04/11 will not work. CC ® will insert a BREAK instruction in the Program memory. The instruc DWDR[7:0] R/W R/W R/W R ATtiny24A/44A/84A R/W R/W R/W R DWDR 151 ...
Page 152
... Page Write operation or by writing the CTPB bit in SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. ATtiny24A/44A/84A 152 The CPU is halted during the Page Erase operation. ...
Page 153
... Note that the Page Erase and Page Write operations Addressing the Flash During SPM BIT 15 ZPCMSB PCMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE The variables used in Figure 18-1 are listed in ATtiny24A/44A/84A Z12 Z11 Z10 ...
Page 154
... Read the FLB from the LPM destination register. If successful, the contents of the destination register are as follows. Bit Rd Refer to ATtiny24A/44A/84A 154 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro- grammed, will be read as one. 7 ...
Page 155
... ZL Preload SPMCSR bits into R16, then write to SPMCSR ldi r16, (1<<RSIG)|(1<<SPMEN) out SPMCSR, r16 ; Issue LPM. Table data will be returned into r17 lpm r17, Z ret See “Code Examples” on page 6. 160. ATtiny24A/44A/84A FHB4 FHB3 FHB2 FHB1 ...
Page 156
... Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. • Bit 5 – RSIG: Read Device Signature Imprint Table Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in ...
Page 157
... During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. 8183D–AVR–04/11 “Device Signature Imprint Table” on page 160 “EEPROM Write Prevents Writing to SPMCSR” on page 154 ATtiny24A/44A/84A for details. 157 for ...
Page 158
... This section describes the different methods for programming ATtiny24A/44A/84A memories. 19.1 Program And Data Memory Lock Bits The ATtiny24A/44A/84A provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in erased to “1” with the Chip Erase command. ...
Page 159
... Fuse Bytes The ATtiny24A/44A/84A have three fuse bytes. describe the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 19-3. Fuse Extended Byte SELFPRGEN Notes: Table 19-4 ...
Page 160
... Most of this memory segment is reserved for internal use, as outlined in Table 19-6. Address 0x00 0x01 0x02 0x03 0x04 0x05 ... 0x2A Notes: ATtiny24A/44A/84A 160 Fuse Low Byte Bit No Description (1) 7 Divide clock by 8 (2) 6 Clock Output Enable ...
Page 161
... ATtiny44A ATtiny84A 19.3.2 Calibration Byte The device signature imprint table of ATtiny24A/44A/84A contains one byte of calibration data for the internal oscillator, as shown in matically written into the OSCCAL register to ensure correct frequency of the calibrated oscillator. Calibration bytes can also be read by the device firmware. See section Signature Data from Software” ...
Page 162
... When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. ATtiny24A/44A/84A 162 Figure 19-1 below. ...
Page 163
... High:> 2 CPU clock cycles for f 19.5.1 Serial Programming Algorithm When writing serial data to the ATtiny24A/44A/84A, data is clocked on the rising edge of SCK. When reading, data is clocked on the falling edge of SCK. See timing details. To program and verify the ATtiny24A/44A/84A in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in 1 ...
Page 164
... Read Signature Byte Read Fuse bits Read Fuse High bits Read Extended Fuse Bits Read Calibration Byte (6) Write Instructions Write Program Memory Page Write EEPROM Memory Write EEPROM Memory Page (page access) ATtiny24A/44A/84A 164 power off. CC Table 19-12 Byte 1 Byte 2 $AC $53 $AC ...
Page 165
... Serial Programming Instruction Byte 3 Byte 4 Adr LSB 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page N-1 Program Memory/ EEPROM Memory ATtiny24A/44A/84A Instruction Format Byte 2 Byte 3 $E0 $00 $A0 $00 $A8 $00 $A4 $00 Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 2 Byte 3 ...
Page 166
... Table 19-14. Pin Values Used to Enter Programming Mode Pin PA0 PA1 PA2 19.7 High-Voltage Serial Programming Algorithm To program and verify the ATtiny24A/44A/84A in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in ATtiny24A/44A/84A 166 High-voltage Serial Programming +11.5 - 12.5V PB3 (RESET) SCI ...
Page 167
... RESET actually reaches 4.5 - 5.5V before giving any serial instructions on CC RESET Pin High-voltage Threshold V HVRST 11.5V 11.5V ATtiny24A/44A/84A to “000”, RESET pin and V reaches at least 1.8V within CC has elapsed. to “000”, RESET pin and V Minimum High-voltage Period for Latching Prog_enable t HVRST 100 ns ...
Page 168
... Programming” cycle to finish. 4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed. 5. End Page Programming by Loading Command “No Operation”. When writing or reading serial data to the ATtiny24A/44A/84A, data is clocked on the rising edge of the serial clock, see page 181 ATtiny24A/44A/84A ...
Page 169
... PROGRAM PCPAGE PCWORD COUNTER PAGE ADDRESS WITHIN THE FLASH PAGE High-voltage Serial Programming Waveforms MSB MSB MSB Table 20-11 on page Table 19-16 on page 170): ATtiny24A/44A/84A WORD ADDRESS WITHIN A PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND LSB LSB LSB 180 ...
Page 170
... Reading the Signature Bytes and Calibration Byte The algorithms for reading the Signature bytes and Calibration byte are shown in page 170. 19.7.10 Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24A/44A/84A Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII ...
Page 171
... Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24A/44A/84A (Continued) Instruction Instr.1/5 SDI 0_0000_0010_00 Load “Read Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_bbbb_bbbb_00 SII 0_0000_1100_00 Read Flash SDO x_xxxx_xxxx_xx Low and High SDI 0_0000_0000_00 Bytes SII 0_0111_1000_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0001_00 Load “ ...
Page 172
... Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24A/44A/84A (Continued) Instruction Instr.1/5 SDI 0_0010_0000_00 Write Lock SII 0_0100_1100_00 Bits SDO x_xxxx_xxxx_xx SDI 0_0000_0100_00 Read Fuse SII 0_0100_1100_00 Low Bits SDO x_xxxx_xxxx_xx SDI 0_0000_0100_00 Read Fuse SII 0_0100_1100_00 High Bits SDO x_xxxx_xxxx_xx SDI ...
Page 173
... V = 5.5V, input low 5.5V, input low CC ATtiny24A/44A/84A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied ...
Page 174
... Values are with external clock using methods described in enabled (PRR = 0xFF) and there is no I/O drive. 10. BOD Disabled. 20.3 Speed The maximum operating frequency of the device depends on V relationship between maximum frequency and V Figure 20-1. ATtiny24A/44A/84A 174 = -40°C to +85°C (Continued) A Condition MHz ...
Page 175
... Fixed voltage within: 1.8V – 5.5V 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage 1.8 - 5.5V CC Min. 0 250 100 100 ATtiny24A/44A/84A Figure 21-109 on page 237 and Accuracy at given voltage Temperature & temperature 25°C Fixed temperature within: -40°C to +85° 2 4 Max ...
Page 176
... V POR V POA SR ON Note: 20.5.2 Brown-Out Detection Table 20-6. BODLEVEL[2:0] Fuses Note: ATtiny24A/44A/84A 176 Reset, Brown-out, and Internal Voltage Characteristics Parameter RESET pin threshold voltage Minimum pulse width on RESET pin Brown-out Detector hysteresis Minimum pulse width on Brown-out Reset Internal bandgap reference voltage Internal bandgap reference ...
Page 177
... V = 4V, REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 200 kHz 4V, REF CC ADC clock = 200 kHz Free Running Conversion 14 50 GND 2.0 1.0 0 ATtiny24A/44A/84A Typ Max Units 10 Bits 2.0 LSB 2.5 LSB 1.5 LSB 2.0 LSB 1.0 LSB 0.5 LSB 2.0 LSB 1.5 LSB 280 µs ...
Page 178
... DIFF Input Bandwidth A External Reference Voltage REF V Internal Voltage Reference INT R Reference Input Resistance REF R Analog Input Resistance AIN ADC Conversion Output ATtiny24A/44A/84A 178 = -40°C to +85°C A Condition Min Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200 kHz Gain = 20x ...
Page 179
... A External Reference Voltage REF V Internal Voltage Reference INT R Reference Input Resistance REF R Analog Input Resistance AIN ADC Conversion Output 8183D–AVR–04/11 ATtiny24A/44A/84A = -40°C to +85°C A Condition Min Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200 kHz Gain = 20x ...
Page 180
... All parameters are based on simulation results and are not tested in production 20.8 Serial Programming Characteristics Figure 20-3. Figure 20-4. SERIAL DATA INPUT SERIAL DATA OUTPUT SERIAL CLOCK INPUT Table 20-11. Serial Programming Characteristics, T Symbol 1/t CLCL t CLCL 1/t CLCL ATtiny24A/44A/84A 180 = -40°C to +85°C A Condition ...
Page 181
... SCI (PB0) Pulse Width Low SDI (PA6), SII (PB1) Valid to SCI (PB0) High SDI (PA6), SII (PB1) Hold after SCI (PB0) High SCI (PB0) High to SDO (PA4) Valid Wait after Instr. 3 for Write Fuse Bits ATtiny24A/44A/84A = -40°C to +85° Min ...
Page 182
... I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules is controlled by the Power Reduction Register. See details. Table 21-1. PRR bit PRTIM1 PRTIM0 PRUSI PRADC Table 21-2 ages and frequencies than those mentioned in the ATtiny24A/44A/84A 182 × × operating voltage load capacitance and f CC ...
Page 183
... MHz. From Table 21-2 on page × ≈ 0,05mA 1 + 0,05 + 0,10 + 0,20 Active Supply Current vs. Low Frequency 0.1 - 1.0 MHz, PRR = 0xFF 0,1 0,2 0,3 0,4 ATtiny24A/44A/84A Current consumption additional to idle mode with external clock Figure 21-57) (see Figure 21-61 183, third column, we see that we need 0,06mA 0,5 0,6 0,7 0,8 Frequency (MHz) and Figure 21-62 Figure 21- ...
Page 184
... Figure 21- Figure 21- ATtiny24A/44A/84A 184 Active Supply Current vs. Frequency MHz, PRR = 0xFF Frequency (MHz) Active Supply Current vs. V Internal RC Oscillator, 8 MHz 1 3 (V) CC 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2 °C 25 ° ...
Page 185
... Figure 21-4. 1,2 0,8 0,6 0,4 0,2 Figure 21-5. 0,14 0,12 0,1 0,08 0,06 0,04 0,02 0 8183D–AVR–04/11 Active Supply Current vs. V Internal RC Oscillator, 1 MHz 1 0 1,5 2 2,5 3 Active Supply Current vs. V Internal RC Oscillator, 128 kHz 1,5 2 2,5 3 ATtiny24A/44A/84A CC 3 3 °C 25 °C -40 °C 5,5 -40 °C 25 °C 85 °C 5,5 185 ...
Page 186
... Current Consumption in Idle Mode Figure 21-6. 0,14 0,12 0,1 0,08 0,06 0,04 0,02 0 Figure 21-7. 4 3,5 3 2,5 2 1,5 1 0,5 0 ATtiny24A/44A/84A 186 Idle Supply Current vs. Low Frequency 0.1 - 1.0 MHz, PRR = 0xFF 0 0,1 0,2 0,3 0,4 Frequency (MHz) Idle Supply Current vs. Frequency MHz, PRR = 0xFF Frequency (MHz) 0,5 0,6 0,7 0,8 0 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2 5.5 V 5.0 V 4.5 V 4.0 V 3 ...
Page 187
... Figure 21-8. 2 1,8 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 0 Figure 21-9. 0,4 0,35 0,3 0,25 0,2 0,15 0,1 0,05 0 8183D–AVR–04/11 Idle Supply Current vs. V Internal RC Oscillator, 8 MHz 1,5 2 2,5 3 Idle Supply Current vs. V Internal RC Oscillator, 1 MHz 1,5 2 2,5 3 ATtiny24A/44A/84A CC 3,5 4 4 3,5 4 4 °C 25 °C -40 °C 5 5,5 85 °C 25 °C -40 °C 5 5,5 187 ...
Page 188
... Figure 21-10. Idle Supply Current vs. V 0,03 0,025 0,02 0,015 0,01 0,005 0 21.2.3 Current Consumption in Power-down Mode Figure 21-11. Power-down Supply Current vs. V 0,8 0,6 0,4 0,2 0 1,5 ATtiny24A/44A/84A 188 CC Internal RC Oscillator, 128 kHz 1,5 2 2,5 3 Watchdog Timer Disabled 2 2,5 3 3 3 (V) CC -40 °C 25 °C 85 °C 5,5 85 °C 25 °C -40 °C 5,5 8183D–AVR–04/11 ...
Page 189
... Figure 21-12. Power-down Supply Current vs 21.2.4 Current Consumption in Reset Figure 21-13. Reset Supply Current vs. V 0,16 0,14 0,12 0,1 0,08 0,06 0,04 0,02 8183D–AVR–04/11 Watchdog Timer Enabled 1,5 2 2,5 3 0.1 - 1.0 MHz, Excluding Current through Reset Pull- 0,1 0,2 0,3 0,4 ATtiny24A/44A/84A CC 3,5 4 4 0,5 0,6 0,7 0,8 Frequency (MHz) -40 °C 25 °C 85 °C 5 5,5 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0,9 1 189 ...
Page 190
... Figure 21-14. Reset Supply Current vs 2,5 2 1,5 1 0,5 0 21.2.5 Current Consumption of Peripheral Units Figure 21-15. ADC Current vs. V 600 500 400 300 200 100 0 ATtiny24A/44A/84A 190 MHz, Excluding Current through Reset Pull- Frequency (MHz MHz Frequency 1 3,5 4 4,5 5 ...
Page 191
... Figure 21-16. AREF Pin Current vs. Pin Voltage 200 180 160 140 120 100 Figure 21-17. Analog Comparator Current vs. V 160 140 120 100 8183D–AVR–04/11 0 1 MHz Frequency 0 1,5 2 2,5 3 ATtiny24A/44A/84A 3,5 4 4,5 5 AREF (V) CC 3 (V) CC 5,5 5,5 191 ...
Page 192
... Figure 21-18. Programming Current vs. V 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 1 Figure 21-19. Brownout Detector Current vs ATtiny24A/44A/84A 192 BOD Level = 1.8V 1 3 (V) CC -40 °C 25 °C 85 °C ...
Page 193
... Figure 21-20. Watchdog Timer Current vs. V 21.2.6 Pull-up Resistors Figure 21-21. Pull-up Resistor Current vs. Input Voltage 8183D–AVR–04/ 1,5 2 2,5 3 I/O Pin 1. 0,2 0,4 0,6 0,8 ATtiny24A/44A/84A CC 3 1,2 1,4 1,6 1,8 V (V) OP -40 °C 25 °C 85 °C 5,5 25 °C -40 °C 85 °C 2 193 ...
Page 194
... Figure 21-22. Pull-up Resistor Current vs. Input Voltage Figure 21-23. Pull-up Resistor Current vs. Input Voltage 160 140 120 100 ATtiny24A/44A/84A 194 I/O Pin 2. I/O Pin ( ( °C 85 °C -40 ° ...
Page 195
... Figure 21-24. Reset Pull-up Resistor Current vs. Reset Pin Voltage Figure 21-25. Reset Pull-up Resistor Current vs. Reset Pin Voltage 8183D–AVR–04/ 1. 0,2 0,4 0 ATtiny24A/44A/84A 1 1,2 1,4 1,6 V (V) RESET (V) RESET 25 °C -40 °C 85 °C 1 °C -40 °C 85 °C 3 195 ...
Page 196
... Figure 21-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage 120 100 21.2.7 Output Driver Strength Figure 21-27. V 1,2 1 0,8 0,6 0,4 0,2 0 ATtiny24A/44A/84A 196 Output Voltage vs. Sink Current OL I/O Pin (V) RESET (mA °C -40 °C 85 ° °C 25 ° ...
Page 197
... Figure 21-28. V 0,6 0,5 0,4 0,3 0,2 0,1 Figure 21-29. V 3,2 2,8 2,6 2,4 2,2 1,8 8183D–AVR–04/11 : Output Voltage vs. Sink Current OL I/O Pin Output Voltage vs. Source Current OH I/O Pin ATtiny24A/44A/84A (mA (mA °C 25 °C -40 ° -40 °C 25 °C 85 ° 197 ...
Page 198
... Figure 21-30. V 5,2 5 4,8 4,6 4,4 4,2 Figure 21-31. V 1,4 1,2 1 0,8 0,6 0,4 0,2 0 ATtiny24A/44A/84A 198 : Output Voltage vs. Source Current OH I/O Pin Output Voltage vs. Sink Current OL Reset Pin as I/ (mA (mA) OL -40 °C 25 °C 85 ° °C 25 °C -40 °C 3 8183D–AVR–04/11 ...
Page 199
... Figure 21-32. V 1,2 0,8 0,6 0,4 0,2 Figure 21-33. V 2,5 1,5 0,5 8183D–AVR–04/11 : Output Voltage vs. Sink Current OL Reset Pin as I/ 0 Output Voltage vs. Source Current OH Reset Pin as I/ 0,2 0,4 0,6 0,8 ATtiny24A/44A/84A 2,5 3 3,5 4 4,5 I (mA 1,2 1,4 1,6 1,8 I (mA °C 25 °C -40 °C 5 -40 °C 25 °C 85 °C 2 199 ...
Page 200
... Figure 21-34. V 4,5 4 3,5 3 2,5 2 1,5 1 0,5 0 21.2.8 Input Threshold and Hysteresis (for I/O Ports) Figure 21-35. V 3,5 3 2,5 2 1,5 1 0,5 0 ATtiny24A/44A/84A 200 : Output Voltage vs. Source Current OH Reset Pin as I/ 0,2 0,4 0,6 0,8 : Input Threshold Voltage vs I/O Pin, Read as ‘1’ 1 1,2 1,4 1,6 1,8 I (mA 3 (V) CC -40 °C 25 °C 85 ° °C 25 ° ...