ATtiny28L Atmel Corporation, ATtiny28L Datasheet
ATtiny28L
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ATtiny28L Summary of contents
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... PDIP, 32-lead TQFP, and 32-pad MLF • Operating Voltages – 1.8V - 5.5V for the ATtiny28V CC – 2.7V - 5.5V for the ATtiny28L CC • Speed Grades – 1.2 MHz for the ATtiny28V – MHz For the ATtiny28L Pin Configurations PDIP RESET 1 28 PA0 PD0 2 27 PA1 PD1 ...
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... Description Block Diagram ATtiny28L/V 2 The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi- tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working registers ...
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... Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier. Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. Figure 2. ATtiny28L/V 3 ...
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... Architectural Overview ATtiny28L/V 4 The fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file – ...
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... OR and all other operations between two registers single register apply to the entire register file. Registers 30 and 31 form a 16-bit pointer (the Z-pointer), which is used for indirect Flash memory and register file access. When the register file is accessed, the contents of R31 are discarded by the CPU. ATtiny28L … ...
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... Status Register Status Register – SREG ATtiny28L/V 6 The AVR status register (SREG) at I/O space location $3F is defined as: Bit $ Read/Write R/W R/W R/W Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers ...
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... Figure 5. Oscillator Connections Note: 1. When using the MCU oscillator as a clock for an external device buffer should be connected as indicated in the figure. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 6. ATtiny28L/V MAX 1 HC BUFFER HC C2 XTAL2 C1 ...
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... External RC Oscillator ATtiny28L/V 8 Figure 6. External Clock Drive Configuration EXTERNAL OSCILLATOR SIGNAL For timing insensitive applications, the external RC configuration shown in Figure 7 can be used. For details on how to choose R and C, see Table 25 on page 56. Figure 7. External RC Configuration XTAL2 NC XTAL1 GND XTAL2 NC XTAL1 GND 1062F– ...
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... MHz, thus tuning to other values is not guaranteed and 25 the pre-programmed calibration byte gives a frequency within ± the nominal frequency. Table 2. Internal RC Oscillator Range OSCCAL Value Min Frequency 0x00 0.6 MHz 0x7F 0.8 MHz 0xFF 1.2 MHz ATtiny28L CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W ...
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... Memories I/O Memory ATtiny28L/V 10 The I/O space definition of the ATtiny28 is shown in Table 3. Table 3. ATtiny28 I/O Space Address Hex Name Function $3F SREG Status Register $1B PORTA Data Register, Port A $1A PACR Port A Control Register $19 PINA Input Pins, Port A $16 PINB Input Pins, Port B $12 PORTD Data Register, Port D ...
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... Figure 8. Direct Single Register Addressing The operand is contained in register d (Rd). Figure 9. Indirect Register Addressing The register accessed is the one pointed to by the Z-register (R31, R30). Figure 10. Direct Register Addressing, Two Registers ATtiny28L/V REGISTERFILE 0 30 Z-Register 31 ...
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... I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction ATtiny28L/V 12 Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 11. I/O Direct Addressing Operand address is contained in six bits of the instruction word the destination or source register address. ...
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... Flash is organized words. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATtiny28 program counter is 10 bits wide, thus addressing the 1K word Flash pro- gram memory. See “Programming the Flash” on page 47 for a detailed description of Flash data downloading. ATtiny28L ...
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... Sleep Modes Idle Mode Power-down Mode ATtiny28L enter the sleep modes, the SE bit in MCUCS must be set (one) and a SLEEP instruc- tion must be executed. The SM bit in the MCUCS register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction enabled interrupt occurs while the MCU sleep mode, the MCU awakes ...
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... V POT Power-on Reset Threshold Voltage (falling) V RESET Pin Threshold Voltage RST Note: 1. The Power-on Reset will not work unless the supply voltage has been below V (falling). ATtiny28L/V DATA BUS MCU Control and Status Register (MCUCS CKSEL[3..0] Delay Counters Full CK ...
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... Power-on Reset ATtiny28L/V 16 Table 5. ATtiny28 Clock Options and Start-up Time CKSEL3..0 Clock Source 1111 External Crystal/Ceramic Resonator 1110 External Crystal/Ceramic Resonator 1101 External Crystal/Ceramic Resonator 1100 External Crystal/Ceramic Resonator 1011 External Crystal/Ceramic Resonator 1010 External Crystal/Ceramic Resonator 1001 External Low-frequency Crystal ...
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... Shorter pulses are not guaranteed to generate a reset. When the applied voltage reaches the Reset Threshold Voltage ( its positive edge, the delay timer starts the MCU after the Time-out RST period (t ) has expired. TOUT ATtiny28L/V decreases below detection level. See CC V RST t TOUT has ...
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... Watchdog Reset ATtiny28L/V 18 Figure 19. External Reset during Operation VCC RESET V RST TIME-OUT INTERNAL RESET When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period (t ) ...
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... To make use of the reset flags to identify a reset condition, the user should read and then clear the flag bits in MCUCS as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. ATtiny28L ...
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... Interrupts Reset and Interrupt Interrupt Handling ATtiny28L/V 20 The ATtiny28 provides five different interrupt sources. These interrupts and the reset vector each have a separate program vector in the program memory space. All the inter- rupts are assigned to individual enable bits. In order to enable the interrupt, both the individual enable bit and the I-bit in the status register (SREG) must be set to one ...
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... This is also the case for the special functions T0, INT0 and INT1. If low-level interrupt is selected, the low level must be held until the completion of the cur- rently executing instruction to generate an interrupt. When this interrupt is enabled, the interrupt will trigger as long as any of the Port B pins are held low. ATtiny28L/V 21 ...
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... Register Description Interrupt Control Register – ICR ATtiny28L/V 22 Bit $06 INT1 INT0 LLIE Read/Write R/W R/W R/W Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and I-bit in the Status Register (SREG) is set (one), the external pin interrupt 1 is enabled ...
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... This flag is always cleared when INT1 is configured as level interrupt. • Bit 6 – INTF0: External Interrupt Flag0 When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt ATtiny28L TOV0 – ...
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... ATtiny28L/V 24 enable bit, INT0 in GIMSK is set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured as level interrupt. ...
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... Output Note: n: 3,1,0, pin number PA2 is the built-in, high-current LED driver and it is always an output pin. The output sig- nal can be modulated with a software programmable frequency. See “Hardware Modulator” on page 39 for further details. ATtiny28L/V Pull-up Comment No Tri-state (high-Z) Yes PAn will source current if ext. pulled low. ...
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... Port A Schematics ATtiny28L/V 26 Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 21. Port A Schematic Diagram (Pins PA0, PA1 and PA3) MOS PULL- UP RESET R PAn WP: WRITE PORTA WD: WRITE DDRA RL: READ PORTA LATCH ...
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... If the interrupt is enabled, the pull-up resistor on PB3 is disabled and PB3 will not give low-level interrupts. • T0 – Port B, Bit 2 T0, Timer/Counter0 Counter source. See the timer description for further details used as the counter source, the pull-up resistor on PB2 is disabled and PB2 will not give low-level interrupts. ATtiny28L the inter ...
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... Port B Schematics ATtiny28L/V 28 • AIN1 – Port B, Bit 1 AIN1, Analog Comparator Negative input. When the on-chip analog comparator is enabled, this pin also serves as the negative input of the comparator. If the analog com- parator is enabled, the pull-up resistors on PB1 and PB0 are disabled and these pins will not give low-level interrupts. • ...
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... UP PB2 RP: READ PORTB PIN Figure 25. PORT B Schematic Diagram (Pins PB3 and PB4) MOS PULL- UP PBn RP: READ PORTB PIN ATtiny28L/V PULL-UP PORT LOW-LEVEL DETECTOR TIMER0 CLOCK SENSE CONTROL SOURCE MUX CS02 CS01 CS00 PULL-UP PORT B INTm ENABLE RP TO LOW-LEVEL DETECTOR ...
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... Port D Port D as General Digital I/O ATtiny28L/V 30 Figure 26. PORT B Schematic Diagram (Pins PB7 - PB5) MOS PULL- UP PBn RP: READ PORT B PIN Port 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for Port D, one each for the Data Register – ...
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... Figure 27. Port D Schematic Diagram (Pins PD7 - PD0) MOS PULL- UP PDn WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ATtiny28L/V RD RESET DDDn C WD RESET PORTDn ...
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... Register Description Port A Data Register – PORTA Port A Control Register – PACR Port A Input Pins Address – PINA Port B Input Pins Address – PINB ATtiny28L/V 32 Bit $1B – – – Read/Write Initial Value Bit $1A – – ...
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... N/A N/A The Port D Input Pins Address (PIND) is not a register; this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read and when reading PIND, the logical values present on the pins are read. ATtiny28L PORTD4 ...
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... Timer/Counter0 Timer/Counter Prescaler ATtiny28L/V 34 The ATtiny28 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. Timer/Counter0 has prescaling selection from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock time base counter with an external pin connection that triggers the counting. ...
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... Table 13. Overflow Output Mode Select OOM01 OOM00 Description 0 0 Timer/Counter0 disconnected from output pin PA2 0 1 Toggle the PA2 output line Clear the PA2 output line to zero Set the PA2 output line to one. ATtiny28L OOM01 OOM00 CS02 CS01 R/W R/W R/W R ...
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... Timer Counter 0 – TCNT0 ATtiny28L/V 36 • Bits – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. Table 14. Clock 0 Prescale Select CS02 CS01 CS00 ...
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... When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared (zero), the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce- dure must be followed: ATtiny28L/V levels. The WDR CC 4 ...
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... ATtiny28L the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical “0” to WDE. This disables the Watchdog. • ...
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... PORTA2 bit or configure OOM00 and OOM01 to set PA2 on the next overflow. If the MODCR register is changed during modulation, the changed value will take effect at the start of the next cycle, producing a glitch-free output. See Figure 31 below and Figure 22 on page 26. ATtiny28L/V PA2 Output 0 Modulated ...
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... ATtiny28L/V 40 Figure 31. The Hardware Modulator FROM PORTA2 WM: WRITE MODCR RM: READ MODCR Figure 32 to Figure 35 show examples on output from the Modulator. Figure 32 also shows the timing for the enable setting signal and for the count enable signal to Timer/Counter0. Figure 32. Modulation with ONTIM = 3, MCONF = 010. ...
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... MHz 38 kHz 4 MHz 38 kHz 455 kHz 455 kHz 1 MHz 455 kHz 1.82 MHz 455 kHz 1.82 MHz 455 kHz 1.8432 MHz 455 kHz 1.8432 MHz 455 kHz 2 MHz 455 kHz ATtiny28L/V % Error in ONTIM Frequency Duty-cycle Value 0.2 25% 2 0.2 33% 3 0.2 50% 5 0.2 67% 3 0.2 75 ...
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... ATtiny28L/V 42 Table 17. Some Common Modulator Configurations (Continued) Crystal/Resonator Carrier Frequency Frequency 2 MHz 455 kHz 2.4576 MHz 455 kHz 2.4576 MHz 455 kHz 3.2768 MHz 455 kHz 3.2768 MHz 455 kHz 3.64 MHz 455 kHz 3.64 MHz 455 kHz 4 MHz 455 kHz 4 MHz 455 kHz ...
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... If the MCONF register is set to 111, the carrier frequency will be equal to the oscillator frequency. Off-time Duty-cycle Min Period X 100% X ONTIM+1 50 (ONTIM+1) 33 (ONTIM+1) 25 ONTIM+1 67 ONTIM+1 75 Reserved X Note ATtiny28L ONTIM1 ONTIM0 MCONF2 MCONF1 R/W R/W R/W R fosc = ----------------------------------------------------- ( ) On-time + Off-time Max Period Comment ...
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... Analog Comparator Register Description Analog Comparator Control and Status Register – ACSR ATtiny28L/V 44 The analog comparator compares the input values on the positive input PB0 (AIN0) and negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output (ACO) is set (one) ...
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... Interrupt Enable bit in the ACSR register. Otherwise, an interrupt can occur when the bits are changed. Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write a one back into ACI read as set, thus clearing the flag. ATtiny28L/V 45 ...
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... Bits Fuse Bits Signature Bytes Calibration Byte ATtiny28L/V 46 The ATtiny28 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 20. The Lock bits can only be erased with the Chip Erase command. ...
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... When pulsing WR or OE, the command loaded determines the action executed. The command is a byte where the different bits are assigned functions, as shown in Table 24. Figure 37. Parallel Programming RDY/BSY XA0 XA1 +12V ATtiny28L/V Parallel Programming 4.5 - 5.5V ATtiny28 +5V PD1 VCC PD2 PB7 - PB0 DATA PD3 ...
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... Enter Programming Mode ATtiny28L/V 48 Table 22. Pin Name Mapping Signal Name in Programming Mode Pin Name RDY/BSY PD1 OE PD2 WR PD3 BS PD4 XA0 PD5 XA1 PD6 DATA PB7 - PB0 . Table 23. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed Load Flash/Signature byte Address (High or low address byte for Flash ...
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... Wait until RDY/BSY goes high to program the next byte. (See Figure 38 for signal waveforms.) F: Load Data High Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data high byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data high byte. G: Write Data High Byte ATtiny28L/V 49 ...
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... Reading the Flash Programming the Fuse Bits Programming the Lock Bits ATtiny28L Set BS to “1”. This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. ...
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... C: Load Address Low Byte ($00). 1. Set OE to “0”, and BS to “1”. The calibration byte can now be read at DATA. 2. Set OE to “1”. Figure 38. Programming the Flash Waveforms DATA $10 ADDR. HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET 12V OE ATtiny28L/V ADDR. LOW DATA LOW 51 ...
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... ATtiny28L/V 52 Figure 39. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET +12V OE 1062F–AVR–07/06 ...
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... WR Pulse Width Low WLWH t WR Low to RDY/BSY Low WLRL t WR Low to RDY/BSY High WLRH t XTAL1 Low to OE Low XLOL t OE Low to DATA Valid OLDV t OE High to DATA Tri-stated OHDZ ATtiny28L/V t XLWL t t XLDX BVWL t WLWH t WLRL t XLOL t OLDV Min Typ 11.5 67 ...
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... V Output Low Voltage OL Port A2 (4) V Output High Voltage OH Ports Input Leakage Current I/O Pin IL I Input Leakage Current I/O Pin IL R I/O Pin Pull-up I/O I Power Supply Current CC ATtiny28L/V 54 *NOTICE: + 0.5V CC Condition Min (Except XTAL) -0.5 XTAL -0.5 (Except XTAL, RESET) 0 XTAL 0 RESET 0. mA, V ...
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... Condition Min -50 2. 4.0V CC may exceed the related specification. OL may exceed the related specification. OH ATtiny28L/V Typ Max 40.0 50.0 750.0 500 3V) under steady-state 5V, 1 3V) under steady-state CC CC Units ...
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... Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL Table 25. External RC Oscillator, Typical Frequencies R [kΩ] 100.0 31.5 6.5 ATtiny28L 1. Min Max Min 0.0 1.2 0.0 833.0 250.0 333.0 100.0 333.0 100.0 1.6 1 [pF] 70.0 20 ...
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... Watchdog Timer. Figure 42. Active Supply Current vs. Frequency ACTIVE SUPPLY CURRENT vs. FREQUENCY 2. 1. ATtiny28L/V = Operating Voltage and f = Average Switching Fre 25˚ ...
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... ATtiny28L/V 58 Figure 43. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 1.5 2 2.5 3 Figure 44. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 1.2MHz INTERNAL RC OSCILLATOR 1 FREQUENCY = 4 MHz T = 25˚ 85˚C A 3 ...
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... DEVICE CLOCKED BY 32 kHz CRYSTAL 4 3.5 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 Figure 46. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY 4.5 4 3.5 3 2.5 2 1 ATtiny28L/V , Device Clocked by External 32 kHz Crystal 25˚C A 3.5 4 4.5 5 5 25˚ ...
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... ATtiny28L/V 60 Figure 47. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 Figure 48. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 1.2MHz INTERNAL RC OSCILLATOR 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 FREQUENCY = 4 MHz T = 85˚C A 3.5 4 4.5 5 5 Device Clocked by Internal Oscillator ˚ ...
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... IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32 kHz CRYSTAL 1.5 2 2.5 3 Figure 50. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 ATtiny28L/V , Device Clocked by External 32 kHz Crystal 85˚ 3.5 4 4.5 5 5 WATCHDOG TIMER DISABLED 3.5 4 4.5 5 5 25˚ ...
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... ATtiny28L/V 62 Figure 51. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs 1.5 2 2.5 3 Analog comparator offset voltage is measured as absolute offset. Figure 52. Analog Comparator Offset Voltage vs. Common Mode Voltage ( 0.5 1 1.5 Common Mode Voltage ( WATCHDOG TIMER ENABLED T = 25˚ ...
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... Figure 53. Analog Comparator Offset Voltage vs. Common Mode Voltage ( 0.5 1 Common Mode Voltage (V) Figure 54. Analog Comparator Input Leakage Current ( -10 0 0.5 1 1.5 2 ATtiny28L 25˚C A 1.5 2 2 2.5 3 3.5 4 4.5 5 5 2.7V 85˚ 25°C) ...
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... ATtiny28L/V 64 Figure 55. Calibrated Internal RC Oscillator Frequency vs. V CALIBRATED RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1.28 1.26 1.24 1.22 1.2 1.18 1.16 1.14 1.12 1.1 2 2.5 3 Figure 56. Watchdog Oscillator Frequency vs. V 1600 1400 1200 1000 800 600 400 200 0 1 3.5 4 4.5 5 5 25˚C A 3.5 4 4.5 5 5 ˚ ˚ ...
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... Figure 57. Pull-up Resistor Current vs. Input Voltage (V 120 T = 25˚C A 100 T = 85˚ 0.5 1 1.5 Figure 58. Pull-up Resistor Current vs. Input Voltage ( 25˚ 85˚ 0.5 1 ATtiny28L 2.5 3 3.5 4 4 2.7V) CC 1.5 2 2 ...
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... ATtiny28L/V 66 Figure 59. I/O Pin Sink Current vs. Output Voltage. All pins except PA2 ( 0.5 1 Figure 60. I/O Pin Source Current vs. Output voltage ( 25˚ 85˚ 0 25˚ 85˚C A 1.5 2 2 ...
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... Figure 61. I/O Pin Sink Current vs. Output Voltage, All Pins Except PA2 ( 0.5 Figure 62. I/O Pin Source Current vs. Output Voltage ( 25˚ 85˚ 0.5 1 ATtiny28L 25˚ 85˚ 1 2.7V) CC 1.5 2 2 2.7V ...
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... ATtiny28L/V 68 Figure 63. PA2 I/O Pin Sink Current vs. Output Voltage (High Current Pin PA2; T 25° 0.5 1 1.5 Figure 64. I/O Pin Input Threshold Voltage vs. V 2.5 2 1.5 1 0 2.5 3 3 25° 4 1062F–AVR–07/ 5.0 ...
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... Figure 65. I/O Pin Input Hysteresis vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 ATtiny28L 25° 4.0 5 ...
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... Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. ATtiny28L/V 70 Bit 6 ...
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... PC ← then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← then PC ← ATtiny28L/V Flags # Clocks Z,C,N,V,H 1 Z,C,N,V,H 1 Z,C,N,V,H ...
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... Set T in SREG CLT Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset ATtiny28L/V 72 Operation Rd ← (Z) (Z) ← ← ← ← ← ← (Z) I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← ...
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... Lead Pitch 0.50mm, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF) 1062F–AVR–07/06 Ordering Code Package ATtiny28L-4AC 32A ATtiny28L-4PC 28P3 ATtiny28L-4MC 32M1-A ATtiny28L-4AI 32A (2) ATtiny28L-4AU 32A ATtiny28L-4PI 28P3 (2) ATtiny28L-4PU 28P3 ATtiny28L-4MI 32M1-A (2) ATtiny28L-4MU 32M1-A ATtiny28V-1AC 32A ATtiny28V-1PC 28P3 ATtiny28V-1MC 32M1-A ATtiny28V-1AI 32A (2) 32A ATtiny28V-1AU ...
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... This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny28L PIN 1 IDENTIFIER ...
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... Orchard Parkway San Jose, CA 95131 R 1062F–AVR–07/06 D PIN PLACES 0º ~ 15º REF eB TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) ATtiny28L COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A – – 4.5724 A1 0.508 – D 34.544 – ...
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... Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R ATtiny28L TITLE 32M1-A, 32-pad 1.0 mm Body, Lead Pitch 0.50 mm, 3 ...
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... Errata All revisions 1062F–AVR–07/06 No known errata. ATtiny28L/V 77 ...
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... Datasheet Revision History Rev – 01/06G Rev – 01/06G Rev – 03/05F ATtiny28L/V 78 Please note that the referring page numbers in this section are referred to this docu- ment. The referring revision in this section are referring to the document revision. 1. Updated chapter layout. 2. Updated “Ordering Information” on page 73. ...
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... Sleep Modes....................................................................................................... 21 Timer/Counter0 ................................................................................... 24 Timer/Counter Prescaler..................................................................................... 24 Watchdog Timer.................................................................................. 27 Calibrated Internal RC Oscillator ...................................................... 29 Hardware Modulator ........................................................................... 30 Analog Comparator ............................................................................ 35 I/O Ports............................................................................................... 37 Port A.................................................................................................................. 37 Port B.................................................................................................................. 40 Port D.................................................................................................................. 43 Memory Programming........................................................................ 45 Program Memory Lock Bits ................................................................................ 45 Fuse Bits............................................................................................................. 45 Signature Bytes .................................................................................................. 45 Calibration Byte .................................................................................................. 45 Programming the Flash ...................................................................................... 45 Parallel Programming ......................................................................................... 46 Parallel Programming Characteristics.............................................. 52 ATtiny28L/V i ...
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... ATtiny28L/V ii Electrical Characteristics................................................................... 53 Absolute Maximum Ratings ................................................................................ 53 DC Characteristics.............................................................................................. 53 External Clock Drive Waveforms ........................................................................ 55 External Clock Drive ........................................................................................... 55 Typical Characteristics ...................................................................... 56 Register Summary .............................................................................. 69 Instruction Set Summary ................................................................... 70 Ordering Information.......................................................................... 72 Packaging Information ....................................................................... 74 32A ..................................................................................................................... 74 28P3 ................................................................................................................... 75 32M1-A ............................................................................................................... 76 Errata ................................................................................................... 77 All revisions......................................................................................................... 77 Datasheet Revision History ............................................................... 78 Rev – 01/06G...................................................................................................... 78 Rev – 03/05F ...................................................................................................... 78 Table of Contents .................................................................................. i 1062F– ...
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