ATtiny28L

Manufacturer Part NumberATtiny28L
ManufacturerAtmel Corporation
ATtiny28L datasheets
 

Specifications of ATtiny28L

Flash (kbytes)2 KbytesPin Count28
Max. Operating Frequency4 MHzCpu8-bit AVR
Hardware Qtouch AcquisitionNoMax I/o Pins11
Ext Interrupts10Usb SpeedNo
Usb InterfaceNoGraphic LcdNo
Video DecoderNoCamera InterfaceNo
Analog Comparators1Resistive Touch ScreenNo
Temp. SensorNoCrypto EngineNo
Sram (kbytes)0.03Self Program MemoryNO
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers132khz RtcNo
Calibrated Rc OscillatorYes  
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Page 16/81

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Power-on Reset
ATtiny28L/V
16
Table 5. ATtiny28 Clock Options and Start-up Time
CKSEL3..0
Clock Source
1111
External Crystal/Ceramic Resonator
1110
External Crystal/Ceramic Resonator
1101
External Crystal/Ceramic Resonator
1100
External Crystal/Ceramic Resonator
1011
External Crystal/Ceramic Resonator
1010
External Crystal/Ceramic Resonator
1001
External Low-frequency Crystal
1000
External Low-frequency Crystal
0111
External RC Oscillator
0110
External RC Oscillator
0101
External RC Oscillator
0100
Internal RC Oscillator
0011
Internal RC Oscillator
0010
Internal RC Oscillator
0001
External Clock
0000
External Clock
Note:
1. Due to limited number of clock cycles in the start-up period, it is recommended that
ceramic resonator be used.
This table shows the start-up times from reset. From Power-down mode, only the clock
counting part of the start-up time is used. The Watchdog oscillator is used for timing the
real-time part of the start-up time. The number WDT oscillator cycles used for each
time-out is shown in Table 6.
Table 6. Number of Watchdog Oscillator Cycles
Time-out
Number of Cycles
4.2 ms
1K
67 ms
16K
The frequency of the Watchdog oscillator is voltage-dependent, as shown in the section
“Typical Characteristics” on page 57.
The device is shipped with CKSEL = 0010.
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-
tion level is nominally 1.4V. The POR is activated whenever V
level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail-
ure in supply voltage.
The Power-on Reset (POR) circuit ensures that the device is reset from power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-
mines the delay for which the device is kept in RESET after V
period of the delay counter can be defined by the user through the CKSEL fuses. The
different selections for the delay period are presented in Table 5. The RESET signal is
Start-up Time at 2.7V
(1)
1K CK
(1)
4.2 ms + 1K CK
(1)
67 ms + 1K CK
16K CK
4.2 ms + 16K CK
67 ms + 16K CK
67 ms + 1K CK
67 ms + 32K CK
6 CK
4.2 ms + 6 CK
67 ms + 6 CK
6 CK
4.2 ms + 6 CK
67 ms + 6 CK
6 CK
4.2 ms + 6 CK
is below the detection
CC
rise. The time-out
CC
1062F–AVR–07/06