ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 16

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ATtiny28L

Manufacturer Part Number
ATtiny28L
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny28L

Flash (kbytes)
2 Kbytes
Pin Count
28
Max. Operating Frequency
4 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
11
Ext Interrupts
10
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Power-on Reset
16
ATtiny28L/V
Table 5. ATtiny28 Clock Options and Start-up Time
Note:
This table shows the start-up times from reset. From Power-down mode, only the clock
counting part of the start-up time is used. The Watchdog oscillator is used for timing the
real-time part of the start-up time. The number WDT oscillator cycles used for each
time-out is shown in Table 6.
Table 6. Number of Watchdog Oscillator Cycles
The frequency of the Watchdog oscillator is voltage-dependent, as shown in the section
“Typical Characteristics” on page 57.
The device is shipped with CKSEL = 0010.
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-
tion level is nominally 1.4V. The POR is activated whenever V
level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail-
ure in supply voltage.
The Power-on Reset (POR) circuit ensures that the device is reset from power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-
mines the delay for which the device is kept in RESET after V
period of the delay counter can be defined by the user through the CKSEL fuses. The
different selections for the delay period are presented in Table 5. The RESET signal is
Time-out
4.2 ms
67 ms
CKSEL3..0
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
1. Due to limited number of clock cycles in the start-up period, it is recommended that
ceramic resonator be used.
Clock Source
External Crystal/Ceramic Resonator
External Crystal/Ceramic Resonator
External Crystal/Ceramic Resonator
External Crystal/Ceramic Resonator
External Crystal/Ceramic Resonator
External Crystal/Ceramic Resonator
External Low-frequency Crystal
External Low-frequency Crystal
External RC Oscillator
External RC Oscillator
External RC Oscillator
Internal RC Oscillator
Internal RC Oscillator
Internal RC Oscillator
External Clock
External Clock
Number of Cycles
1K
16K
(1)
(1)
(1)
1K CK
4.2 ms + 1K CK
67 ms + 1K CK
16K CK
4.2 ms + 16K CK
67 ms + 16K CK
67 ms + 1K CK
67 ms + 32K CK
6 CK
4.2 ms + 6 CK
67 ms + 6 CK
6 CK
4.2 ms + 6 CK
67 ms + 6 CK
6 CK
4.2 ms + 6 CK
Start-up Time at 2.7V
CC
is below the detection
CC
rise. The time-out
1062F–AVR–07/06

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