ATtiny28L

Manufacturer Part NumberATtiny28L
ManufacturerAtmel Corporation
ATtiny28L datasheets
 

Specifications of ATtiny28L

Flash (kbytes)2 KbytesPin Count28
Max. Operating Frequency4 MHzCpu8-bit AVR
Hardware Qtouch AcquisitionNoMax I/o Pins11
Ext Interrupts10Usb SpeedNo
Usb InterfaceNoGraphic LcdNo
Video DecoderNoCamera InterfaceNo
Analog Comparators1Resistive Touch ScreenNo
Temp. SensorNoCrypto EngineNo
Sram (kbytes)0.03Self Program MemoryNO
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers132khz RtcNo
Calibrated Rc OscillatorYes  
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Page 20/81

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Interrupts
Reset and Interrupt
Interrupt Handling
ATtiny28L/V
20
The ATtiny28 provides five different interrupt sources. These interrupts and the reset
vector each have a separate program vector in the program memory space. All the inter-
rupts are assigned to individual enable bits. In order to enable the interrupt, both the
individual enable bit and the I-bit in the status register (SREG) must be set to one.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 7. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
Table 7. Reset and Interrupt Vectors
Vector
Program
No.
Address
Source
1
$000
RESET
2
$001
INT0
3
$002
INT1
4
$003
Input Pins
TIMER0,
5
$004
OVF0
6
$005
ANA_COMP
The most typical and general program setup for the Reset and Interrupt vector
addresses are:
Address
Labels
Code
$000
rjmp
$001
rjmp
$002
rjmp
$003
rjmp
$004
rjmp
$005
rjmp
;
$006
MAIN:
<instr>
xxx
The ATtiny28 has one 8-bit Interrupt Control Register (ICR).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the program counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
Interrupt Definition
Hardware Pin, Power-on Reset and
Watchdog Reset
External Interrupt Request 0
External Interrupt Request 1
Low-level Input on Port B
Timer/Counter0 Overflow
Analog Comparator
Comments
RESET
; Reset handler
EXT_INT0
; IRQ0 handler
EXT_INT1
; IRQ1 handler
LOW_LEVEL
; Low level input handler
TIM0_OVF
; Timer0 overflow handle
ANA_COMP
; Analog Comparator handle
; Main program start
1062F–AVR–07/06