ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 20
Manufacturer Part Number
Specifications of ATtiny28L
Max. Operating Frequency
Hardware Qtouch Acquisition
Max I/o Pins
Resistive Touch Screen
Self Program Memory
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Mpu / Mmu
no / no
Calibrated Rc Oscillator
Reset and Interrupt
The ATtiny28 provides five different interrupt sources. These interrupts and the reset
vector each have a separate program vector in the program memory space. All the inter-
rupts are assigned to individual enable bits. In order to enable the interrupt, both the
individual enable bit and the I-bit in the status register (SREG) must be set to one.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 7. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
Table 7. Reset and Interrupt Vectors
The most typical and general program setup for the Reset and Interrupt vector
The ATtiny28 has one 8-bit Interrupt Control Register (ICR).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the program counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
Hardware Pin, Power-on Reset and
External Interrupt Request 0
External Interrupt Request 1
Low-level Input on Port B
; Reset handler
; IRQ0 handler
; IRQ1 handler
; Low level input handler
; Timer0 overflow handle
; Analog Comparator handle
; Main program start