ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 20

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ATtiny28L

Manufacturer Part Number
ATtiny28L
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny28L

Flash (kbytes)
2 Kbytes
Pin Count
28
Max. Operating Frequency
4 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
11
Ext Interrupts
10
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Interrupts
Reset and Interrupt
Interrupt Handling
20
ATtiny28L/V
The ATtiny28 provides five different interrupt sources. These interrupts and the reset
vector each have a separate program vector in the program memory space. All the inter-
rupts are assigned to individual enable bits. In order to enable the interrupt, both the
individual enable bit and the I-bit in the status register (SREG) must be set to one.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 7. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
Table 7. Reset and Interrupt Vectors
The most typical and general program setup for the Reset and Interrupt vector
addresses are:
The ATtiny28 has one 8-bit Interrupt Control Register (ICR).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the program counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
Vector
Address
$000
$001
$002
$003
$004
$005
;
$006
No.
1
2
3
4
5
6
Labels
MAIN:
Program
Address
$000
$001
$002
$003
$004
$005
Code
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
<instr>
Source
RESET
INT0
INT1
Input Pins
TIMER0,
OVF0
ANA_COMP
xxx
RESET
EXT_INT0
EXT_INT1
LOW_LEVEL
TIM0_OVF
ANA_COMP
Interrupt Definition
Hardware Pin, Power-on Reset and
Watchdog Reset
External Interrupt Request 0
External Interrupt Request 1
Low-level Input on Port B
Timer/Counter0 Overflow
Analog Comparator
Comments
; Reset handler
; IRQ0 handler
; IRQ1 handler
; Low level input handler
; Timer0 overflow handle
; Analog Comparator handle
; Main program start
1062F–AVR–07/06

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