ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 21

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ATtiny28L

Manufacturer Part Number
ATtiny28L
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny28L

Flash (kbytes)
2 Kbytes
Pin Count
28
Max. Operating Frequency
4 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
11
Ext Interrupts
10
Usb Speed
No
Usb Interface
No
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.03
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
1
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Interrupt Response Time
External Interrupt
Low-level Input Interrupt
1062F–AVR–07/06
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled or the
flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the status register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles the program vector address for the actual interrupt
handling routine is executed. During this 4-clock-cycle period, the program counter (10
bits) is pushed onto the stack. The vector is normally a relative jump to the interrupt rou-
tine, and this jump takes two clock cycles. If an interrupt occurs during execution of a
multi-cycle instruction, this instruction is completed before the interrupt is served. If an
interrupt occurs when the MCU is in sleep mode, the interrupt execution response time
is increased by four clock cycles.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the program counter (10 bits) is popped back from the stack, and the I-flag
in SREG is set. When AVR exits from an interrupt, it will always return to the main pro-
gram and execute one more instruction before any pending interrupt is served.
The external interrupt is triggered by the INT pins. Observe that, if enabled, the interrupt
will trigger even if the INT pin is configured as an output. This feature provides a way of
generating a software interrupt. The external interrupt can be triggered by a falling or ris-
ing edge, a pin change or a low level. This is set up as indicated in the specification for
the Interrupt Control Register (ICR). When the external interrupt is enabled and is con-
figured as level-triggered, the interrupt will trigger as long as the pin is held low.
The external interrupt is set up as described in the specification for the Interrupt Control
Register (ICR).
The low-level interrupt is triggered by setting any of the Port B pins low. However, if any
Port B pins are used for other special features, these pins will not trigger the interrupt.
For example, if the analog comparator is enabled, a low level on PB0 or PB1 will not
cause an interrupt. This is also the case for the special functions T0, INT0 and INT1. If
low-level interrupt is selected, the low level must be held until the completion of the cur-
rently executing instruction to generate an interrupt. When this interrupt is enabled, the
interrupt will trigger as long as any of the Port B pins are held low.
ATtiny28L/V
21

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