ATtiny28L

Manufacturer Part NumberATtiny28L
ManufacturerAtmel Corporation
ATtiny28L datasheets
 


Specifications of ATtiny28L

Flash (kbytes)2 KbytesPin Count28
Max. Operating Frequency4 MHzCpu8-bit AVR
Hardware Qtouch AcquisitionNoMax I/o Pins11
Ext Interrupts10Usb SpeedNo
Usb InterfaceNoGraphic LcdNo
Video DecoderNoCamera InterfaceNo
Analog Comparators1Resistive Touch ScreenNo
Temp. SensorNoCrypto EngineNo
Sram (kbytes)0.03Self Program MemoryNO
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers132khz RtcNo
Calibrated Rc OscillatorYes  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Page 21
22
Page 22
23
Page 23
24
Page 24
25
Page 25
26
Page 26
27
Page 27
28
Page 28
29
Page 29
30
Page 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 30/81

Download datasheet (664Kb)Embed
PrevNext
Port D
Port D as General Digital I/O
ATtiny28L/V
30
Figure 26. PORT B Schematic Diagram (Pins PB7 - PB5)
MOS
PULL-
UP
PBn
RP:
READ PORT B PIN
n:
5 - 7
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.
Three I/O memory address locations are allocated for Port D, one each for the Data
Register – PORTD, $12, Data Direction Register – DDRD, $11 and the Port D Input Pins
– PIND, $10. The Port D Input Pins address is read-only, while the Data Register and
the Data Direction Register are read/write.
The Port D output buffers can sink 10 mA. As inputs, Port D pins that are externally
pulled low will source current if the pull-up resistors are activated.
All eight pins in Port D have equal functionality when used as digital I/O pins.
PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin.
If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn
is configured as an input pin. If PDn is set (one) when configured as an input pin, the
MOS pull-up resistor is activated. To switch the pull-up resistor off, the PDn has to be
cleared (zero), or the pin has to be configured as an output pin. The port pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Table 12. DDDn Bits on Port D Pins
DDDn
PORTDn
I/O
0
0
Input
0
1
Input
1
0
Output
1
1
Output
Note:
n: 7,6,...,0, pin number
PULL-UP PORT B
RP
TO LOW-LEVEL DETECTOR
Pull-up
Comment
No
Tri-state (high-Z)
Yes
PDn will source current if ext. pulled low
No
Push-pull Zero Output
NO
Push-pull One Output
1062F–AVR–07/06