ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 30
Manufacturer Part Number
Specifications of ATtiny28L
Max. Operating Frequency
Hardware Qtouch Acquisition
Max I/o Pins
Resistive Touch Screen
Self Program Memory
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Mpu / Mmu
no / no
Calibrated Rc Oscillator
Port D as General Digital I/O
Figure 26. PORT B Schematic Diagram (Pins PB7 - PB5)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.
Three I/O memory address locations are allocated for Port D, one each for the Data
Register – PORTD, $12, Data Direction Register – DDRD, $11 and the Port D Input Pins
– PIND, $10. The Port D Input Pins address is read-only, while the Data Register and
the Data Direction Register are read/write.
The Port D output buffers can sink 10 mA. As inputs, Port D pins that are externally
pulled low will source current if the pull-up resistors are activated.
All eight pins in Port D have equal functionality when used as digital I/O pins.
PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin.
If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn
is configured as an input pin. If PDn is set (one) when configured as an input pin, the
MOS pull-up resistor is activated. To switch the pull-up resistor off, the PDn has to be
cleared (zero), or the pin has to be configured as an output pin. The port pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Table 12. DDDn Bits on Port D Pins
n: 7,6,...,0, pin number
READ PORT B PIN
5 - 7
PDn will source current if ext. pulled low
Push-pull Zero Output
Push-pull One Output
TO LOW-LEVEL DETECTOR
PULL-UP PORT B