ATtiny28L

Manufacturer Part NumberATtiny28L
ManufacturerAtmel Corporation
ATtiny28L datasheets
 


Specifications of ATtiny28L

Flash (kbytes)2 KbytesPin Count28
Max. Operating Frequency4 MHzCpu8-bit AVR
Hardware Qtouch AcquisitionNoMax I/o Pins11
Ext Interrupts10Usb SpeedNo
Usb InterfaceNoGraphic LcdNo
Video DecoderNoCamera InterfaceNo
Analog Comparators1Resistive Touch ScreenNo
Temp. SensorNoCrypto EngineNo
Sram (kbytes)0.03Self Program MemoryNO
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers132khz RtcNo
Calibrated Rc OscillatorYes  
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Page 37/81

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Watchdog Timer
Register Description
Watchdog Timer Control
Register – WDTCR
1062F–AVR–07/06
The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the
Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in
Table 15. See characterization data for typical values at other V
(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle
periods can be selected to determine the reset period. If the reset period expires without
another Watchdog reset, the ATtiny28 resets and executes from the reset vector. For
timing details on the Watchdog reset, refer to page 18.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 30. Watchdog Timer
Oscillator
1 MHz at V
= 5V
CC
350 kHz at V
= 3V
CC
110 kHz at V
= 2V
CC
Bit
7
6
5
$01
Read/Write
R
R
R
Initial Value
0
0
0
• Bits 7..5 - Res: Reserved Bits
These bits are reserved bits in the ATtiny28 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared
(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the
WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-
dure must be followed:
ATtiny28L/V
levels. The WDR
CC
4
3
2
1
WDTOE
WDE
WDP2
WDP1
R/W
R/W
R/W
R/W
0
0
0
0
0
WDP0
WDTCR
R/W
0
37