ATtiny28L

Manufacturer Part NumberATtiny28L
ManufacturerAtmel Corporation
ATtiny28L datasheets
 


Specifications of ATtiny28L

Flash (kbytes)2 KbytesPin Count28
Max. Operating Frequency4 MHzCpu8-bit AVR
Hardware Qtouch AcquisitionNoMax I/o Pins11
Ext Interrupts10Usb SpeedNo
Usb InterfaceNoGraphic LcdNo
Video DecoderNoCamera InterfaceNo
Analog Comparators1Resistive Touch ScreenNo
Temp. SensorNoCrypto EngineNo
Sram (kbytes)0.03Self Program MemoryNO
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers132khz RtcNo
Calibrated Rc OscillatorYes  
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Page 44/81

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Analog Comparator
Register Description
Analog Comparator Control
and Status Register – ACSR
ATtiny28L/V
44
The analog comparator compares the input values on the positive input PB0 (AIN0) and
negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher
than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output
(ACO) is set (one). The comparator can trigger a separate interrupt exclusive to the ana-
log comparator. The user can select interrupt triggering on comparator output rise, fall or
toggle. A block diagram of the comparator and its surrounding logic is shown in Figure
36.
Figure 36. Analog Comparator Block Diagram
PB0
PB1
Bit
7
6
5
$08
ACD
ACO
Read/Write
R/W
R
R
Initial Value
1
0
X
• Bit 7 – ACD: Analog Comparator Disable
When this bit is set (one), the power to the analog comparator is switched off. This bit
can be set at any time to turn off the analog comparator. When changing the ACD bit,
the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise, an interrupt can occur when the bit is changed. To use the analog compara-
tor, the user must clear this bit.
• Bit 6 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and will always read as zero.
• Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
4
3
2
1
0
ACI
ACIE
ACIS1
ACIS0
R/W
R/W
R
R/W
R/W
0
0
0
0
0
ACSR
1062F–AVR–07/06