ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 45
Manufacturer Part Number
Specifications of ATtiny28L
Max. Operating Frequency
Hardware Qtouch Acquisition
Max I/o Pins
Resistive Touch Screen
Self Program Memory
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Mpu / Mmu
no / no
Calibrated Rc Oscillator
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logical “1” to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the ana-
log comparator interrupt is activated. When cleared (zero), the interrupt is disabled.
• Bit 2 – RES: Reserved Bit
This bit is a reserved bit in the ATtiny28 and will always read as zero.
• Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events trigger the Analog Comparator Interrupt.
The different settings are shown in Table 19.
Table 19. ACIS1/ACIS0 Settings
Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write
a one back into ACI if it is read as set, thus clearing the flag.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-
abled by clearing its Interrupt Enable bit in the ACSR register. Otherwise, an interrupt can
occur when the bits are changed.
Comparator Interrupt on Output Toggle
Comparator Interrupt on Falling Output Edge
Comparator Interrupt on Rising Output Edge