ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 5
Manufacturer Part Number
Specifications of ATtiny28L
Max. Operating Frequency
Hardware Qtouch Acquisition
Max I/o Pins
Resistive Touch Screen
Self Program Memory
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Mpu / Mmu
no / no
Calibrated Rc Oscillator
ALU – Arithmetic Logic
Subroutine and Interrupt
r a t e i n t e r r u p t v e c t o r i n t h e i n t e r r u p t v e c t o r t a b le a t t h e b e g i n n i n g o f t h e
program memory. The different interrupts have priority in accordance with their interrupt
vector position. The lower the interrupt vector address, the higher the priority.
The high-performance AVR ALU operates in direct connection with all the 32 general-
purpose working registers. Within a single clock cycle, ALU operations between regis-
ters in the register file are executed. The ALU operations are divided into three main
categories – arithmetic, logic and bit functions. Some microcontrollers in the AVR prod-
uct family feature a hardware multiplier in the arithmetic part of the ALU.
The ATtiny28 uses a 3-level-deep hardware stack for subroutines and interrupts. The
hardware stack is 10 bits wide and stores the program counter (PC) return address
while subroutines and interrupts are executed.
RCALL instructions and interrupts push the PC return address onto stack level 0, and
the data in the other stack levels 1 - 2 are pushed one level deeper in the stack. When a
RET or RETI instruction is executed the returning PC is fetched from stack level 0, and
the data in the other stack levels 1 - 2 are popped one level in the stack.
If more than three subsequent subroutine calls or interrupts are executed, the first val-
ues written to the stack are overwritten.
Figure 4 shows the structure of the 32 general-purpose registers in the CPU.
Figure 4. AVR CPU General-purpose Working Registers
All the register operating instructions in the instruction set have direct and single cycle
access to all registers. The only exception are the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the
LDI instruction for load immediate constant data. These instructions apply to the second
half of the registers in the register file – R16..R31. The general SBC, SUB, CP, AND,
OR and all other operations between two registers or on a single register apply to the
entire register file.
Registers 30 and 31 form a 16-bit pointer (the Z-pointer), which is used for indirect Flash
memory and register file access. When the register file is accessed, the contents of R31
are discarded by the CPU.
R30 (Z-Register low byte)
R31(Z-Register high byte)