ATtiny28L

Manufacturer Part NumberATtiny28L
ManufacturerAtmel Corporation
ATtiny28L datasheets
 

Specifications of ATtiny28L

Flash (kbytes)2 KbytesPin Count28
Max. Operating Frequency4 MHzCpu8-bit AVR
Hardware Qtouch AcquisitionNoMax I/o Pins11
Ext Interrupts10Usb SpeedNo
Usb InterfaceNoGraphic LcdNo
Video DecoderNoCamera InterfaceNo
Analog Comparators1Resistive Touch ScreenNo
Temp. SensorNoCrypto EngineNo
Sram (kbytes)0.03Self Program MemoryNO
Dram MemoryNoNand InterfaceNo
PicopowerNoTemp. Range (deg C)-40 to 85
I/o Supply Class1.8 to 5.5Operating Voltage (vcc)1.8 to 5.5
FpuNoMpu / Mmuno / no
Timers132khz RtcNo
Calibrated Rc OscillatorYes  
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Status Register
Status Register – SREG
ATtiny28L/V
6
The AVR status register (SREG) at I/O space location $3F is defined as:
Bit
7
6
5
$3F
I
T
H
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable register is cleared (zero), none of the interrupts are enabled inde-
pendent of the individual interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s comple-
ment overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the
Instruction Set description for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
See the Instruction Set description for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation. See the
Instruction Set description for detailed information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-
tion Set description for detailed information.
Note that the status register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
4
3
2
1
S
V
N
Z
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1062F–AVR–07/06
0
C
SREG
0