# ATtiny28L Atmel Corporation, ATtiny28L Datasheet - Page 71

#### ATtiny28L

Manufacturer Part Number

ATtiny28L

Description

Manufacturer

Atmel Corporation

#### Specifications of ATtiny28L

Flash (kbytes)

2 Kbytes

Pin Count

28

Max. Operating Frequency

4 MHz

Cpu

8-bit AVR

Hardware Qtouch Acquisition

No

Max I/o Pins

11

Ext Interrupts

10

Usb Speed

No

Usb Interface

No

Graphic Lcd

No

Video Decoder

No

Camera Interface

No

Analog Comparators

1

Resistive Touch Screen

No

Temp. Sensor

No

Crypto Engine

No

Sram (kbytes)

0.03

Self Program Memory

NO

Dram Memory

No

Nand Interface

No

Picopower

No

Temp. Range (deg C)

-40 to 85

I/o Supply Class

1.8 to 5.5

Operating Voltage (vcc)

1.8 to 5.5

Fpu

No

Mpu / Mmu

no / no

Timers

1

32khz Rtc

No

Calibrated Rc Oscillator

Yes

Instruction Set Summary

1062F–AVR–07/06

Mnemonic

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

SUB

SUBI

SBC

SBCI

AND

ANDI

OR

ORI

EOR

COM

NEG

SBR

CBR

INC

DEC

TST

CLR

SER

BRANCH INSTRUCTIONS

RJMP

RCALL

RET

RETI

CPSE

CP

CPC

CPI

SBRC

SBRS

SBIC

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

Operands

Rd, Rr

Rd, Rr

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Rd

Rd, K

Rd, K

Rd

Rd

Rd

Rd

Rd

k

k

Rd, Rr

Rd, Rr

Rd, Rr

Rd, K

Rr, b

Rr, b

P, b

P, b

s, k

s, k

k

k

k

k

k

k

k

k

k

k

k

k

k

k

k

k

k

k

Description

Add Two Registers

Subtract Two Registers

Subtract Constant from Register

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Logical AND Register and Constant

Exclusive OR Registers

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Decrement

Clear Register

Set Register

Relative Jump

Relative Subroutine Call

Subroutine Return

Compare, Skip if Equal

Compare

Compare with Carry

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Add with Carry Two Registers

Logical AND Registers

Logical OR Registers

Logical OR Register and Constant

Increment

Test for Zero or Minus

Interrupt Return

Skip if Bit in Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Greater or Equal, Signed

Branch if Less than Zero, Signed

Branch if T-flag Set

Branch if T-flag Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

Operation

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rd ← Rd • Rr

Rd ← Rd • K

Rd ← Rd v Rr

Rd ← Rd v K

Rd ← Rd ⊕ Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Rd ← Rd • (FFh - K)

Rd ← Rd + 1

Rd ← Rd - 1

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

PC ← PC + k + 1

PC ← PC + k + 1

PC ← STACK

PC ← STACK

if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

Rd - Rr - C

Rd - K

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (P(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ← PC + k + 1

if (SREG(s) = 0) then PC ← PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

Flags

Z,C,N,V,H

Z,C,N,V,H

Z,C,N,V,H

Z,C,N,V,H

Z,C,N,V,H

Z,N,V

Z,N,V

Z,N,V

Z,N,V

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Z,N,V

Z,N,V

Z,N,V

Z,N,V

Z,N,V

None

None

None

None

I

None

Z N,V,C,H

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

Z,C,N,V,H

Z,N,V,C,H

Z,N,V,C,H

ATtiny28L/V

# Clocks

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1/2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

3

4

4

1

1

1

71