ATtiny48 Atmel Corporation, ATtiny48 Datasheet

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... MHz @ 2.7 5.5V – – – MHz @ 4.5 5.5V • Low Power Consumption – Active Mode: 1 MHz, 1.8V: 240 µA – Power-Down Mode: 0.1 µA at 1.8V ® 8-Bit Microcontroller 2 C Compatible) 8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash ATtiny48/88 Rev. 8008H–AVR–04/11 ...

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... Pin Configurations Figure 1-1. Pinout of ATtiny48/88 (PCINT19/INT1) PD3 (PCINT20/T0) PD4 (PCINT26) PA2 VCC GND (PCINT27) PA3 (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT19/INT1) PD3 (PCINT20/T0) PD4 VCC GND (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT21/T1) PD5 NOTE: Bottom pad should be soldered to ground. Table 1- ATtiny48/88 ...

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... The 8008H–AVR–04/11 even if the ADC is not used. If the ADC is used recom- CC through a low-pass filter, as described in CC 172. : PC7, PC[5:0] and (in 32-lead pack- CC “Alternate Functions of Port B” on page ATtiny48/88 “Analog Noise . CC 3 ...

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... The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in 75. ATtiny48/88 4 Table 22-3 on page 209. Shorter pulses are not guaranteed to “ ...

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... Overview The ATtiny48/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

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... Programmable Flash on a monolithic chip, the Atmel ATtiny48/ powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny48/88 AVR is supported by a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits. ...

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... Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.5 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. 8008H–AVR–04/11 ATtiny48/88 ® ® and QMatrix acquisi- 7 ...

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... While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. ATtiny48/88 8 Block Diagram of the AVR Architecture ...

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... The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 – 0x5F. In addition, the ATtiny48/88 has Extended I/O space from 0x60 – 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used ...

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... One 16-bit output operand and one 16-bit result input Figure 4-2 Figure 4-2. 7 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. ATtiny48/88 10 shows the structure of the 32 general purpose working registers in the CPU. General Purpose Working Registers 0 Addr. ...

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... In some 8008H–AVR–04/11 Figure 4-2, each register is also assigned a data memory address, mapping them The X-, Y-, and Z-registers R27 R29 R31 ATtiny48/88 Figure 4- R26 R28 R30 0 0 ...

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... Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Lock Bits LB2 or LB1 are pro- ATtiny48/88 12 Table 5-2 on page ...

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... When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the 8008H–AVR–04/11 for details. “Interrupts” on page 52 for more information. ATtiny48/88 “Lock Bits, Fuse Bits and “Interrupts” on page 52. The list also 13 ...

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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny48/ store SREG value ; disable interrupts during timed sequence ...

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... SP7 SP6 SP5 SP4 R/W R/W R/W R/W RAMEND RAMEND RAMEND RAMEND R/W R/W R/W R ⊕ V ATtiny48/ RAMEND RAMEND R R R/W R – – SP9 SP8 SP3 SP2 SP1 SP0 R/W R/W R/W R/W RAMEND RAMEND RAMEND RAMEND ...

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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATtiny48/88 16 8008H–AVR–04/11 ...

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... All memory spaces are linear and regular. 5.1 Program Memory (Flash) ATtiny48/88 contains 4/8K byte of on-chip, in-system reprogrammable Flash memory for pro- gram storage. Flash memories are non-volatile, i.e. they retain stored information even when not powered. Since all AVR instructions are bits wide, the Flash is organized as 4096/8192 x 16 bits. ...

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... I/O registers starting at 0x20. See “Instruction Set Summary” on page ATtiny48/88 18 shows how the data memory and register files of ATtiny48/88 are organized. These Layout of Data Memory and Register Area. Memory Area General purpose register file I/O register file Extended I/O register file ...

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... ATtiny48/88 also contains three general purpose I/O registers that can be used for storing any information. See GPIOR0, GPIOR1 and GPIOR2 in general purpose I/O registers are particularly useful for storing global variables and status flags, since they are accessible to bit-specific instructions such as SBI, CBI, SBIC, SBIS, SBRC, and SBRS ...

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... Figure 5-2. 5.3 Data Memory (EEPROM) ATtiny48/88 contains 64 bytes of non-volatile data memory. This EEPROM is organized as a separate data space, in which single bytes can be read and written. All access registers are located in the I/O space. The EEPROM memory layout is summarised in Table 5-3. Device ATtiny48/88 The internal 8MHz oscillator is used to time EEPROM operations. The frequency of the oscillator ...

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... Before writing data to EEPROM the target location must be erased. This can be done either in the same operation or as part of a split operation. Writing to an unerased EEPROM location will result in corrupted data. 8008H–AVR–04/11 ATtiny48/88 Table 5-4 on page 26. Write and erase 21 ...

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... BOD detection levels are not sufficient for the design, an external reset circuit for low V used. Provided that supply voltage is sufficient, an EEPROM write operation will be completed even when a reset occurs. ATtiny48/ the EEPROM data can be corrupted because the supply voltage is CC can be CC 8008H– ...

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... Wait for completion of previous write */ while(EECR & (1<<EEPE Set Programming mode */ EECR = (0<<EEPM1)|(0<<EEPM0) /* Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); See “About Code Examples” on page ATtiny48/ ...

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... Wait for completion of previous write */ while(EECR & (1<<EEPE)) /* Set up address register */ EEAR = ucAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; } Note: ATtiny48/88 24 r16, EEDR See “About Code Examples” on page ; See “About Code Examples” on page 7. 7. ...

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... R R R/W R MSB R/W R/W R/W R – – EEPM1 EEPM0 R R R/W R ATtiny48/ – – – – EEAR3 EEAR2 EEAR1 EEAR0 R/W R/W R/W R LSB R/W R/W R/W ...

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... Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the ATtiny48/88 26 EEPROM Programming Mode Bits and Programming Times ...

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... This register may be used freely for storing any kind of data. 8008H–AVR–04/ MSB R/W R/W R/W R MSB R/W R/W R/W R MSB R/W R/W R/W R ATtiny48/ LSB R/W R/W R/W R LSB R/W R/W R/W R LSB R/W R/W R/W R GPIOR2 ...

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... I/O clock is halted. Also note that the start condition detection of the Two-Wire Interface module is asynchronous, meaning TWI address recognition works in all sleep modes (even when clk ATtiny48/88 28 presents the principal clock systems in the AVR and their distribution. All of the clocks 36 ...

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... For all fuses “1” means unprogrammed while “0” means programmed. 2. The device is shipped with this option selected MHz frequency exceeds the specification of the device (depends on V can be programmed in order to divide the internal frequency by 8. “Fuse Bits” on page 30. ATtiny48/88 page 30) Table 6-1. Frequency – ...

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... The accuracy of this calibration is shown as Factory calibration in Table 22-1 on page By changing the OSCCAL register from SW, see page 34 possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in ATtiny48/88 30 External Clock Drive Configuration EXTERNAL CLOCK SIGNAL ...

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... System Clock Prescaler The ATtiny48/88 has a system clock prescaler, and the system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page system clock frequency and the power consumption when the requirement for processing power 8008H– ...

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... The delay (t oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in ATtiny48/ clk I/O Table 6-6 on page 35 ...

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... SUT[1: rise time. If this is not possible, an internal or external Brown-out Detection circuit should ATtiny48/88 “Watchdog Oscillator Frequency vs. VCC” on page 246. Number of WDT Cycles Typical Time-out 0 4K (4,096) 8K (8,192) Reserved Reserved before it releases the reset, and the time-out ...

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... Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if ATtiny48/ ...

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... ATtiny48/88 CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 35 ...

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... Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk ATtiny48/88 36 for more details. presents the different clock systems in the ATtiny48/88, and their distribu- Active Clock Domains and Wake-up Sources in the Different Sleep Modes Active Clock Domain X 1. For INT1 and INT0, only level interrupt for a summary ...

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... MCU Control Register” on page 8008H–AVR–04/11 , clk , and clk , while allowing the other clocks to run. I/O CPU FLASH “Clock Sources” on page 40. Writing this bit to one turns off the BOD in ATtiny48/88 “External Interrupts” on page 53 29. Table 20-4 on page level has CC 37 ...

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... If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consump- tion. Refer to ATtiny48/88 38 40. for details on ADC operation. ...

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... Sleep Mode Select SM0 Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Reserved ATtiny48/88 ) are stopped, the input buffers of the device will ADC and – – SM1 SM0 R R R/W R Table 7-2. ...

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... Bits – Res: Reserved These bits are reserved and will always read zero. • Bit 5 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. ATtiny48/ – ...

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... When waking up the SPI again, the SPI should be re initialized to ensure proper operation. • Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot be used when the ADC is shut down. 8008H–AVR–04/11 ATtiny48/88 41 ...

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... This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in ATtiny48/88 42 Figure 8-1 shows the reset circuit. ...

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... Reset Sources The ATtiny48/88 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the required pulse length. ...

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... Figure 8-4. 8.2.3 Brown-Out Detection ATtiny48/88 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...

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... Figure 8-6. 8.3 Internal Voltage Reference ATtiny48/88 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 8.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...

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... Watchdog Timer ATtiny48/88 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...

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... Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. See ”About Code Examples” on page 7. ATtiny48/88 47 ...

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... Note: Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period. ATtiny48/88 48 (1) r16, (1<<WDCE) | (1<<WDE) Got four cycles to set the new values from here - r16, (1< ...

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... WDIF WDIE WDP3 WDCE R/W R/W R/W R ATtiny48/ WDRF BORF EXTRF PORF R/W R/W R/W R/W See Bit Description WDE WDP2 WDP1 WDP0 R/W R/W R/W R MCUSR WDTCSR 49 ...

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... The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 8-2 on page Table 8-2. WDP3 ATtiny48/88 50 Watchdog Timer Configuration WDE WDIE Mode 0 0 Stopped 0 1 Interrupt Mode 1 0 System Reset Mode ...

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... Notes: 8008H–AVR–04/11 Watchdog Timer Prescale Select (Continued) WDP2 WDP1 WDP0 selected, one of the valid settings below 0b1010 will be used. ATtiny48/88 Number of Typical Time-out at WDT Oscillator Cycles (1) Reserved ...

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... Interrupts This section describes the specifics of interrupt handling in ATtiny48/88. For a general explana- tion of the AVR interrupt handling, refer to 9.1 Interrupt Vectors Table 9-1. Vector No case the program never enables an interrupt source, the Interrupt Vectors will not be used and, consequently, regular program code can be placed at these locations ...

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... A typical and general setup for interrupt vector addresses in ATtiny48/88 is shown in the pro- gram example below. Assembly Code Example .org 0x0000 RESET: Note: 9.2 External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT[27:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT[27:0] pins are configured as outputs ...

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... Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter- ATtiny48/88 54 “EICRA – External Interrupt Control Register A” on page 28 ...

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... The low level of INT1 generates an interrupt request. 1 Any logical change on INT1 generates an interrupt request. 0 The falling edge of INT1 generates an interrupt request. 1 The rising edge of INT1 generates an interrupt request. Table 9-3. The value on the INT0 pin is sampled before detecting edges. ATtiny48/ ISC11 ISC10 ISC01 ISC00 ...

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... Initial Value • Bits 7:2 – Res: Reserved Bits These bits are unused in ATtiny48/88, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter- nal pin interrupt is enabled ...

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... The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register. 8008H–AVR–04/ – – – – ATtiny48/ PCIE3 PCIE2 PCIE1 PCIE0 R/W R/W R/W R PCICR 57 ...

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... Bits 3:0 – PCINT[27:24]: Pin Change Enable Mask 27:24 Each PCINT[27:24] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[27:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[27:24] is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny48/ – ...

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... R/W R/W R/W R PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATtiny48/ PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W R/W R PCINT3 PCINT2 PCINT1 PCINT0 ...

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... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATtiny48/88 60 and Ground as indicated in CC for a complete list of parameters. ...

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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 77, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATtiny48/88 Figure 10-2 shows a func- PUD Q D DDxn ...

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... Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11 intermediate step. ATtiny48/88 62 R16 R17 out DDRx, r16 ...

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... PINxn Register bit and the preceding latch con- SYSTEM CLK XXX SYNC LATCH PINxn r17 Figure 10-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of ATtiny48/88 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No ...

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... Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out ; Insert nop for synchronization nop ; Read port pins in ... Note: ATtiny48/88 64 SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 (1) r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) PORTB,r16 ...

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... Insert nop for synchronization*/ __no_operation(); /* Read port pins */ i = PINB; ... Figure 10-2, the digital input signal can be clamped to ground at the input of the /2. CC “Alternate Port Functions” on page or GND is not recommended, since this may cause excessive currents if the pin is CC ATtiny48/88 65. Figure 10-6 Figure 10-2 can be overridden by 65 ...

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... Figure 10-6. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: ATtiny48/88 66 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn 1 0 DIEOExn DIEOVxn 1 SLEEP 0 Pxn PULL-UP OVERRIDE ENABLE ...

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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATtiny48/88 Fig- 67 ...

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... Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATtiny48/88 68 Port A Pins Alternate Functions Alternate Function PA3 PCINT27 (Pin Change Interrupt 27) PA2 PCINT26 (Pin Change Interrupt 26) ADC7 (ADC Input Channel 7) PA1 PCINT25 (Pin Change Interrupt 25) ADC6 (ADC Input Channel 6) ...

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... SS (SPI Bus Master Slave select) OC1B (Timer/Counter1 Output Compare Match B Output) PCINT2 (Pin Change Interrupt 2) OC1A (Timer/Counter1 Output Compare Match A Output) PCINT1 (Pin Change Interrupt 1) ICP1 (Timer/Counter1 Input Capture Input) CLKO (Divided System Clock Output) PCINT0 (Pin Change Interrupt 0) ATtiny48/88 Table 10-5. 69 ...

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... PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source. Table 10-6 shown in MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATtiny48/88 70 and Table 10-7 relate the alternate functions of Port B to the overriding signals Figure 10-6 on page 66 ...

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... OC1B PCINT3 • PCIE0 PCINT2 • PCIE0 1 1 PCINT3 INPUT PCINT2 INPUT SPI SLAVE INPUT SPI SS – – ATtiny48/88 PB5/SCK/ PB4/MISO/ PCINT5 PCINT4 SPE • MSTR SPE • MSTR PORTB5 • PUD PORTB4 • PUD SPE • MSTR SPE • MSTR ...

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... PC5 can also be used as ADC input Channel 5. Note that ADC input channel 5 uses digital power. ATtiny48/88 72 Port C Pins Alternate Functions Alternate Function PCINT15 (Pin Change Interrupt 15) ...

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... PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. • ADC0/PCINT8 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source. 8008H–AVR–04/11 ATtiny48/88 73 ...

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... Note: Table 10-10. Overriding Signals for Alternate Functions in PC[3:0] Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATtiny48/88 74 and Table 10-10 relate the alternate functions of Port C to the overriding signals Figure 10-6 on page 66. Overriding Signals for Alternate Functions in PC[6:4] PC6/RESET/ PC7/PCINT15 PCINT14 0 RSTDISBL 0 ...

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... PCINT21 (Pin Change Interrupt 21) T0 (Timer/Counter 0 External Counter Input) PD4 PCINT20 (Pin Change Interrupt 20) INT1 (External Interrupt 1 Input) PD3 PCINT19 (Pin Change Interrupt 19) INT0 (External Interrupt 0 Input) PD2 PCINT18 (Pin Change Interrupt 18) PD1 PCINT17 (Pin Change Interrupt 17) PD0 PCINT16 (Pin Change Interrupt 16) ATtiny48/88 Table 10-11. 75 ...

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... PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source. Table 10-12 shown in Table 10-12. Overriding Signals for Alternate Functions PD[7:4] Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATtiny48/88 76 and Table 10-13 relate the alternate functions of Port D to the overriding signals Figure 10-6 on page 66. PD7/AIN1/PCINT23 PD6/AIN0/PCINT22 ...

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... PUD R R/W R/W R for more details about this feature BBMD BBMC BBMB BBMA R/W R/W R/W R “Break-Before-Make Switching” on page ATtiny48/88 PD1/PCINT17 PD0/PCINT16 PCINT17 • PCIE2 PCINT16 • PCIE2 1 1 PCINT17 INPUT PCINT16 INPUT – – 4 ...

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... Bit 0x03 (0x23) Read/Write Initial Value 10.4.9 PORTC – The Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 10.4.10 DDRC – The Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value ATtiny48/88 78 “Configuring the Pin” on page ...

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... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATtiny48/ PINC3 PINC2 PINC1 PINC0 N/A N/A N/A N PORTD3 PORTD2 PORTD1 PORTD0 R/W R/W R/W R DDD3 DDD2 DDD1 DDD0 ...

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... Timer/Counter number (in this case 0) and a lower case “x” replaces the Output Compare Unit (in this case Compare Unit A or Compare Unit B). However, when using the regis- ATtiny48/88 80 “Pinout of ATtiny48/88” on page 2. CPU accessible I/O Registers, including I/O “PRR – Power Reduction Register” on page 40 Count ...

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... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. “Timer/Counter0 and Timer/Counter1 Prescalers” on page DATA BUS count TCNTn Control Logic clear ATtiny48/ 117. TOVn (Int.Req.) Clock Select Edge Detector ...

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... Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial- ATtiny48/88 82 Increment or decrement TCNT0 by 1. Clear TCNT0 (set all bits to zero). ...

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... TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 11-4. CTC Mode, Timing Diagram TCNTn Period 8008H–AVR–04/11 “Timer/Counter Timing Diagrams” on page Figure ATtiny48/88 84. 11-4. The counter value (TCNT0) OCnx Interrupt Flag Set 83 ...

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... TCNTn TOVn Figure 11-6 Figure 11-6. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 11-7 mode. ATtiny48/88 84 Figure 11-5 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) MAX - 1 ...

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... OCF0A and the clearing of TCNT0 in CTC mode where OCR0A caler (f /8) clk_I/O I/O Tn /8) I/O TOP - – – – Table 11-2. Modes of operation supported by the Timer/Counter unit are: Normal ATtiny48/88 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP – CTC0 CS02 CS01 R R/W R/W R “ ...

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... OCR0A – Output Compare Register A Bit 0x27 (0x47) Read/Write Initial Value The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt. ATtiny48/88 86 CTC Mode Bit Description Timer/Counter CTC0 Mode of Operation 0 ...

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... – – – – ATtiny48/ R/W R/W R/W R – OCIE0B OCIE0A TOIE0 R R/W R/W R – OCF0B OCF0A TOV0 ...

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... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. See Table ATtiny48/88 88 11-2, “CTC Mode Bit Description” on page 86. ...

Page 89

... Figure 12-1. Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Table 10-5 on page 69 1. Refer to Figure 1-1 on page 2, Timer/Counter1 pin placement and description. ATtiny48/88 (1) TOVn (Int.Req.) Control Logic Clock Select clk Tn Edge Tn Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...

Page 90

... BOTTOM MAX TOP ATtiny48/88 90 “Pinout of ATtiny48/88” on page “Register Description” on page “PRR – Power Reduction Register” on page 40 97.. The compare match event will also set the Compare Match 161.) The Input Capture unit includes a digital filtering unit (Noise The counter reaches the BOTTOM when it becomes 0x0000. ...

Page 91

... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATtiny48/88 91 ...

Page 92

... Restore global interrupt flag */ SREG = sreg; return i; } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATtiny48/88 92 (1) (1) 1. See ”About Code Examples” on page 7. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” ...

Page 93

... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATtiny48/88 93 ...

Page 94

... The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM1[3:0]) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms ATtiny48/88 94 “Timer/Counter0 and Timer/Counter1 Prescalers” on page shows a block diagram of the counter and its surroundings ...

Page 95

... I/O bit location. 8008H–AVR–04/11 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ATtiny48/88 “Modes of Operation” on page 100. Figure 12-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise ...

Page 96

... When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter- rupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. ATtiny48/88 96 91. “Accessing 16-bit Registers” ...

Page 97

... DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATtiny48/88 100.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn[3:0] COMnx[1:0] ...

Page 98

... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x[1:0] bits are not double buffered together with the compare value. Changing the COM1x[1:0] bits will take effect immediately. ATtiny48/88 98 91. “Accessing 16-bit Registers” ...

Page 99

... Note that some COM1x[1:0] bit settings are reserved for certain modes of operation. The COM1x[1:0] bits have no effect on the Input Capture unit. 8008H–AVR–04/11 Waveform D Generator OCnx D PORT D DDR See “Register Description” on page 110. ATtiny48/88 Figure 12 Table 12-2, Table 12-3 and Table 12-4 shows a ...

Page 100

... The OCR1A or ICR1 define the top value for the counter, hence also its res- olution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. ATtiny48/88 100 Table 12-2 on page 110, and for phase correct and phase and frequency correct PWM refer to 111. (See “ ...

Page 101

... OCR1A is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATtiny48/88 Figure 12-6. The counter value (TCNT1) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA[1: clk_I/O ⋅ OCRnA 1 + 101 ...

Page 102

... Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. ATtiny48/88 102 log R ...

Page 103

... TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is 8008H–AVR–04/11 f clk_I ---------------------------------- - OCnxPWM ⋅ TOP when OCR1A is set to zero (0x0000). This feature clk_I/O ATtiny48/88 Table on page 110). The actual ) 103 ...

Page 104

... OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord- ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. ATtiny48/88 104 ( ) ...

Page 105

... The dual-slope operation gives a lower maximum operation fre- quency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. 8008H–AVR–04/11 Figure 12-8 f clk_I --------------------------- - OCnxPCPWM ⋅ ⋅ TOP ATtiny48/88 illustrates, changing the Table on page 111). 105 ...

Page 106

... Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. ATtiny48/88 106 12-9). R ...

Page 107

... The actual OC1x value will only be visible on the port pin if the data direction f OCnxPFCPWM Figure 12-10 shows a timing diagram for the setting of OCF1x. ATtiny48/88 f clk_I/O = --------------------------- - ⋅ ⋅ ...

Page 108

... Figure 12-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. ATtiny48/88 108 OCRnx - 1 OCRnx OCRnx Value shows the same timing data, but with the prescaler enabled ...

Page 109

... Old OCRnx Value shows the same timing data, but with the prescaler enabled. clk I/O clk Tn /8) I/O TOP - 1 TOP - 1 (FPWM) (if used Old OCRnx Value ATtiny48/88 TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value ...

Page 110

... When the OC1A or OC1B is connected to the pin, the function of the COM1x[1:0] bits is depen- dent of the WGM1[3:0] bits setting. WGM1[3:0] bits are set to a Normal or a CTC mode (non-PWM). Table 12-2. COM1A1/COM1B1 Table 12-3 PWM mode. Table 12-3. COM1A1/COM1B1 Note: ATtiny48/88 110 COM1A1 COM1A0 COM1B1 R/W R/W ...

Page 111

... Fast PWM, 10-bit 0 PWM, Phase & Frequency Correct 1 PWM, Phase & Frequency Correct 0 PWM, Phase Correct 1 PWM, Phase Correct 0 CTC 1 (Reserved) 0 Fast PWM 1 Fast PWM ATtiny48/88 for more details. 12-5. Update of x TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate ...

Page 112

... See TCCR1A Register description. • Bits 2:0 – CS1[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 12-10 and Table 12-6. CS12 ATtiny48/88 112 (See “Modes of Operation” on page ICNC1 ICES1 – WGM13 R/W R/W ...

Page 113

... External clock source on T1 pin. Clock on rising edge FOC1A FOC1B – – R/W R TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R ATtiny48/ – – – – R/W R/W R/W R See “Accessing 16-bit TCCR1C ...

Page 114

... High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. 12.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register Bit (0x6F) Read/Write Initial Value • Bits 7:6 – Res: Reserved Bits These bits are reserved and will always read zero. ATtiny48/88 114 R/W R/W R/W R/W 0 ...

Page 115

... Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. 8008H–AVR–04/11 46.) is executed when the TOV1 Flag, located in TIFR1, is set – – ICF1 – R ATtiny48/ – OCF1B OCF1A TOV1 R R/W R/W R TIFR1 115 ...

Page 116

... TOV1 Flag is set when the timer overflows. Refer to Flag behavior when using another WGM1[3:0] bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATtiny48/88 116 Table 12-5 on page 111 for the TOV1 ...

Page 117

... Alternatively, one of four taps from the prescaler can be used CLK_I/O /1024. CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk Synchronization ATtiny48/88 CLK_I/O pulse for each positive (CSn[2: negative Edge Detector share the /8, f /64, CLK_I/O Figure 13-1 ). The latch ...

Page 118

... PSRSYNC bit is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. ATtiny48/88 118 < f /2) given a 50% duty cycle. Since the edge detector uses ...

Page 119

... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 8008H–AVR–04/11 ATtiny48/88 119 ...

Page 120

... Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 14.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATtiny48/88 and peripheral devices or between several AVR devices. Figure 14-1. SPI Block Diagram /2/4/8/16/32/64/128 Note: ATtiny48/88 120 (1) MSB ...

Page 121

... SPI clock should never exceed f 8008H–AVR–04/11 “PRR – Power Reduction Register” on page 40 MSB MASTER LSB 8 BIT SHIFT REGISTER SPI ATtiny48/88 must be written to zero to Figure MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER ...

Page 122

... SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for transmission complete sbis SPSR,SPIF rjmp Wait_Transmit ret Note: ATtiny48/88 122 Table 14-1 on page 122. For more details on automatic port overrides, refer to 65. (1) SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1 ...

Page 123

... Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret ; Wait for reception complete sbis SPSR,SPIF rjmp SPI_SlaveReceive ; Read received data and return in r16,SPDR ret 1. See ”About Code Examples” on page 7. ATtiny48/88 123 ...

Page 124

... The MSTR bit in SPCR is cleared and the SPI system becomes a Slave result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. 2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. ATtiny48/88 124 (1) ; ...

Page 125

... CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 8008H–AVR–04/11 Figure 14-4. MSB Bit 6 Bit 5 LSB Bit 1 Bit 2 MSB Bit 6 LSB Bit 1 ATtiny48/88 Bit 4 Bit 3 Bit 2 Bit 1 Bit 3 Bit 4 Bit 5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 2 Bit 3 Bit 4 Bit 5 Figure ...

Page 126

... Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to marized below: Table 14-3. ATtiny48/88 126 127, as done in Table 14-2 Setting SPI Mode using Control Bits CPOL and CPHA ...

Page 127

... Relationship Between SCK and the Oscillator Frequency SPR1 SPIF WCOL – ATtiny48/88 and Figure 14-4 for an example. The CPOL Trailing Edge Sample Setup Setup Sample SPR0 SCK Frequency osc osc osc 128 ...

Page 128

... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATtiny48/88 is also used for program memory and EEPROM down- loading or uploading. See 14.5.3 SPDR – SPI Data Register ...

Page 129

... TWI protocol. Figure 15-1. TWI Bus Interconnection SDA SCL 8008H–AVR–04/ compatible 2 C compatible and, with reservations, SMBus compatible (see 156). Device 1 Device 3 Device 2 ATtiny48/ ........ R1 R2 Device n “Compati- 129 ...

Page 130

... Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 15-2. Data Validity ATtiny48/88 130 TWI Terminology Description The device that initiates and terminates a transmission and generates the SCL clock ...

Page 131

... STOP condition REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. Figure 15-4. Address Packet Format SDA SCL 8008H–AVR–04/11 START STOP Addr MSB 1 START ATtiny48/88 START REPEATED START Addr LSB R STOP ACK 9 131 ...

Page 132

... Master consequence, the Slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle. Figure 15-6 between the SLA+R/W and the STOP condition, depending on the software protocol imple- mented by the application software. ATtiny48/88 132 Data MSB 1 2 Data Byte shows a typical data transmission ...

Page 133

... Master B SCL Bus Line 8008H–AVR–04/11 Addr MSB Addr LSB R/W ACK SLA+R/W TA low TB low Masters Start Counting Low Period ATtiny48/88 Data MSB Data LSB ACK Data Byte TA high TB high Masters Start Counting High Period STOP 133 ...

Page 134

... This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. ATtiny48/88 134 START Master A Loses ...

Page 135

... Control Bus Interface Unit START / STOP Spike Suppression Control Address/Data Shift Arbitration detection Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator ATtiny48/88 Figure 15-9. All registers SDA Spike Filter Bit Rate Generator Prescaler Bit Rate Register Ack (TWBR) Control Unit ...

Page 136

... Upon an address match, the Control Unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sleep ATtiny48/88 136 160. In high-speed mode the TWI uses the system clock, whereas in normal ...

Page 137

... Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example imple- menting the desired behavior is also presented. 8008H–AVR–04/ simple example of how the application can interface to the TWI hardware. In ATtiny48/88 137 ...

Page 138

... TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However important ATtiny48/88 138 5. Check TWSR to see if SLA+W was sent and ACK received. ...

Page 139

... TWCR, r16 wait1: in r16,TWCR 2 sbrs r16,TWINT rjmp wait1 8008H–AVR–04/11 C Example TWCR = (1<<TWINT)|(1<<TWSTA)| (1<<TWEN) while (!(TWCR & (1<<TWINT))) ; ATtiny48/88 Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted 139 ...

Page 140

... TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used the application software that decides which modes are legal. ATtiny48/88 140 C Example if ((TWSR & ...

Page 141

... TWINT Flag is set. The Table 15-2 to Table 15-5. Note that the prescaler bits are masked to zero in 15-11). In order to enter a Master mode, a START condition must be transmitted. Device 1 Device 2 Device 3 MASTER SLAVE TRANSMITTER RECEIVER ATtiny48/ ........ Device 141 ...

Page 142

... A REPEATED START condition is generated by writing the following value to TWCR: TWCR value After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again new Slave without transmitting a STOP condition. Repeated START enables ATtiny48/88 142 TWINT TWEA TWSTA ...

Page 143

... No TWDR action TWDR action TWDR action ATtiny48/88 TWE Next Action Taken by TWI Hardware A X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+W will be transmitted; ACK or NOT ACK will be received X SLA+R will be transmitted; Logic will switch to Master Receiver mode ...

Page 144

... The format of the following address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. ATtiny48/88 144 MT S ...

Page 145

... TWSTO Table 15-3. Received data can be read from the TWDR Register when the TWINT TWINT TWEA TWSTA TWSTO TWINT TWEA TWSTA TWSTO ATtiny48/ ........ Device n R1 TWWC TWEN – Table 15-2). In order to enter MR mode, TWWC TWEN – ...

Page 146

... SLA+R has been transmitted; NOT ACK has been received 0x50 Data byte has been received; ACK has been returned 0x58 Data byte has been received; NOT ACK has been returned ATtiny48/88 146 Application Software Response To TWCR To/from TWDR STA STO TWIN ...

Page 147

... DATA From master to slave From slave to master n 15-15). All the status codes mentioned in this section assume that the prescaler bits Device 1 Device 2 Device 3 SLAVE MASTER RECEIVER TRANSMITTER ATtiny48/88 A DATA A P $50 $ $10 Other master A continues $38 To corresponding states in slave mode ...

Page 148

... Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these Sleep modes. ATtiny48/88 148 TWA6 TWA5 ...

Page 149

... No action ATtiny48/88 TWE Next Action Taken by TWI Hardware A 0 Data byte will be received and NOT ACK will be returned 1 Data byte will be received and ACK will be returned 0 Data byte will be received and NOT ACK will be returned 1 ...

Page 150

... Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure are zero or are masked to zero. Figure 15-17. Data Transfer in Slave Transmitter Mode SDA SCL ATtiny48/88 150 S SLA W A $60 A $68 General Call ...

Page 151

... Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 8008H–AVR–04/11 TWA6 TWA5 TWA4 TWA3 Device’s Own Slave Address TWINT TWEA TWSTA TWSTO ATtiny48/88 TWA2 TWA1 TWA0 TWGCE TWWC TWEN – TWIE Table 15-5. 151 ...

Page 152

... Data byte in TWDR has been transmitted; NOT ACK has been received 0xC8 Last data byte in TWDR has been transmitted (TWEA = “0”); ACK has been received ATtiny48/88 152 Application Software Response To TWCR To/from TWDR STA STO TWIN T Load data byte or ...

Page 153

... Application Software Response To TWCR To/from TWDR STA STO TWIN No TWDR action No TWCR action No TWDR action 0 1 ATtiny48/88 DATA A DATA $B8 $C0 $C8 Any number of data bytes A and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the 2-Wire Serial Bus. The ...

Page 154

... The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a Slave Receiver. ATtiny48/88 154 Master Transmitter SLA+W ...

Page 155

... SLA Arbitration lost in SLA Own No Address / General Call received Yes Write 68/78 Direction Read ATtiny48/ ........ Device Data Arbitration lost in Data 38 TWI bus will be released and not addressed slave mode will be entered A START condition will be transmitted when the bus becomes free ...

Page 156

... TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati- cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag ATtiny48/88 156 2 ...

Page 157

... A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. 8008H–AVR–04/11 ATtiny48/88 157 ...

Page 158

... The application designer should mask the pres- caler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. ATtiny48/88 158 ...

Page 159

... Rate Generator Unit” on page TWD7 TWD6 TWD5 TWD4 R/W R/W R/W R TWA6 TWA5 TWA4 TWA3 R/W R/W R/W R ATtiny48/88 Prescaler Value 135. The value of TWPS1:0 is used TWD3 TWD2 TWD1 TWD0 R/W R/W R/W R TWA2 TWA1 TWA0 TWGCE R/W R/W ...

Page 160

... I/O clock frequency, clk frequency clk been selected as source clock, the user must set the prescaler to scale the system clock (and, hence, the I/O clock) down to 4 MHz. For more information about clock systems, see System” on page ATtiny48/88 160 ...

Page 161

... ADC MULTIPLEXER (1) OUTPUT 1. See Table 16-1 on page 161. 2. Refer to Figure 1-1 on page 2 and placement. Analog Comparator Multiplexed Input ADEN MUX[2:0] x xxx 1 xxx 0 000 0 001 ATtiny48/88 for more details. (2) Table 10-11 on page 75 for Analog Comparator pin Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 Table 161 ...

Page 162

... Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 – 2 clock cycles. ATtiny48/88 162 Analog Comparator Multiplexed Input (Continued) ADEN MUX[2:0] ...

Page 163

... ACIS1/ACIS0 Settings ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle. 1 Reserved 0 Comparator Interrupt on Falling Output Edge. 1 Comparator Interrupt on Rising Output Edge – – – – ATtiny48/ – – AIN1D AIN0D R R R/W R DIDR1 163 ...

Page 164

... Sleep Mode Noise Canceler 17.2 Overview ATtiny48/88 features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). The ADC is wired to a nine-channel analog multiplexer, which allows the ADC to measure the volt- age at six (or eight, in 32-lead/pad/ball packages) single-ended input pins and from one internal, single-ended voltage channel coming from the internal temperature sensor. Single-ended volt- age inputs are referred to 0V (GND) ...

Page 165

... ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER REFERENCE BANDGAP SENSOR INPUT MUX for more details. supply pin and the internal 1.1V voltage reference. CC ATtiny48/88 ADC CONVERSION COMPLETE IRQ 15 ADC CTRL. & STATUS ADC DATA REGISTER REGISTER (ADCSRA) (ADCH/ADCL) PRESCALER CONVERSION LOGIC SAMPLE & HOLD ...

Page 166

... Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. ATtiny48/88 166 “PRR – Power Reduction Register” on page 40). A single conver- ...

Page 167

... Figure 17-3. ADC Prescaler 8008H–AVR–04/11 ADTS[2:0] ADIF SOURCE EDGE DETECTOR SOURCE n ADSC ADEN Reset START CK ADPS0 ADPS1 ADPS2 ATtiny48/88 PRESCALER START ADATE CONVERSION LOGIC 7-BIT ADC PRESCALER ADC CLOCK SOURCE CLK ADC 167 ...

Page 168

... ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. Figure 17-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL ATtiny48/88 168 Figure 17-4 below. First Conversion ...

Page 169

... Sample & Prescaler Hold Reset MUX and REFS Update Figure One Conversion 12 13 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete ATtiny48/88 One Conversion Conversion Complete 17-7. Next Conversion Sign and MSB of Result LSB of Result Sample & ...

Page 170

... In Free Running mode, always select the channel before starting the first conversion. The chan- nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel ATtiny48/88 170 Table 17-1 ...

Page 171

... ADC. Single ended REF will result in codes close to 0x3FF. V REF ) through an internal amplifier. BG /2) should not be present. The user is advised to remove high fre- ADC ATtiny48/88 can be selected as either REF Figure 17-8 An analog 171 ...

Page 172

... Keep analog tracks well away from high-speed switching digital tracks. • If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress. • The analog supply voltage pin ( Figure 17-9. ADC Power Connections ATtiny48/88 172 I IH ADCn I ...

Page 173

... LSB). Ideal value: 0 LSB. Figure 17-10. Offset Error Output Code 8008H–AVR–04/11 Section 17.7 on page 171. This is especially the case when system clock frequency Section 17.12 on page 175. A good system design with properly placed, external Offset Error ATtiny48/ steps REF n -1. Ideal ADC Actual ADC V ...

Page 174

... Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 17-12. Integral Non-linearity (INL) Output Code ATtiny48/88 174 Gain Error Ideal ADC ...

Page 175

... ADC8 channel. Selecting the ADC8 channel by writing the MUX[3:0] bits in 8008H–AVR–04/11 Output Code 0x3FF 1 LSB 0x000 0 ADC is the voltage on the selected input pin and V IN and Table 17-4 on page ATtiny48/88 V Input Voltage REF ⋅ V 1024 IN = -------------------------- V REF the selected voltage reference (see REF 177) ...

Page 176

... This bit select the voltage reference for the ADC, as shown in during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Table 17-3. REFS0 0 1 ATtiny48/88 176 Temperature vs. Sensor Output Voltage (Typical Case) -40°C 230 LSB Table 17-2 are typical values. However, due to process variation the ...

Page 177

... After switching to internal voltage reference the ADC requires a settling time of 1ms before measurements are stable. Conversions starting before this may not be reliable. The ADC must be enabled during the settling time. ATtiny48/88 “ADCL and ADCH – The ADC Data Register” on Table 17-4 ...

Page 178

... When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter- rupt is activated. • Bits 2:0 – ADPS[2:0]: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 17-5. ADPS2 ATtiny48/88 178 ADEN ADSC ADATE ADIF R/W R/W ...

Page 179

... – ACME – – ATtiny48/88 Division Factor 32 64 128 – – ADC9 ADC8 ADC3 ADC2 ADC1 ADC0 ...

Page 180

... The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[7:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATtiny48/88 180 ADC Auto Trigger Source Selections ...

Page 181

... Figure 18-1. The debugWIRE Setup Figure 18-1 connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. 8008H–AVR–04/11 dW dW(RESET) GND shows the schematic of a target MCU, with debugWIRE enabled, and the emulator ATtiny48/88 1.8 - 5.5V VCC 181 ...

Page 182

... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATtiny48/88 182 will not work. CC ® ...

Page 183

... SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 8008H–AVR–04/11 ATtiny48/88 183 ...

Page 184

... Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 19-1. Addressing the Flash During SPM Z - REGISTER Note: ATtiny48/88 184 Z15 ...

Page 185

... Fuse High byte FHB7 FHB6 FHB5 FHB4 Table 20-3 on page 189 for detailed description and mapping of the Fuse Extended FEB7 FEB6 FEB5 FEB4 ATtiny48/ – – LB2 LB1 Table 20-5 on page 190 FLB3 FLB2 FLB1 FLB0 3 ...

Page 186

... Bit 7 – Res: Reserved Bit This bit is reserved and will always read zero. • Bit 6 – RWWSB: Read-While-Write Section Busy This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero in ATtiny48/88. ATtiny48/88 186 , the Flash program can be corrupted because the supply voltage is ...

Page 187

... Page Write, the SELFPRGEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect. 8008H–AVR–04/11 “Reading the Fuse and Lock Bits from Software” on page 185 ATtiny48/88 for 187 ...

Page 188

... Notes: Lock bits can be erased to “1” with the Chip Erase command, only. The ATtiny48/88 has no separate Boot Loader section. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed (“0”), otherwise it is disabled. ATtiny48/88 188 Lock Bit Byte ...

Page 189

... Fuse Bits The ATtiny48/88 has three Fuse bytes. of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 20-3. Fuse Extended Byte – – – – ...

Page 190

... Calibration Byte The ATtiny48/88 has a byte calibration value for the internal oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automati- cally written into the OSCCAL Register to ensure correct frequency of the calibrated oscillator. ...

Page 191

... External Programming This section describes how to program and verify Flash memory, EEPROM, lock bits, and fuse bits in ATtiny48/88. 21.1 Memory Parametrics Flash memory parametrics are summarised in Table 21-1. Device ATtiny48 ATtiny88 EEPROM parametrics are summarised in Table 21-2. Device ATtiny48 ATtiny88 21.2 Parallel Programming Parallel programming signals and connections are illustrated in Figure 21-1. Parallel Programming Signals 8008H– ...

Page 192

... The XA1/XA0 pins determine the action executed when the CLKI pin is given a positive pulse. The bit coding is shown in Table 21-5. XA1 ATtiny48/88 192 Table 21-3, below. Pins not listed in the table are referenced by pin Pin Name Mapping Pin Name PD1 PD2 ...

Page 193

... CC Table 21-4 on page 192 to 0V. CC and GND and as soon as V reaches 0.9 – 1.1V, apply 11.5 – 12.5V to RESET actually reaches 4.5 -5.5V before giving any parallel programming CC ATtiny48/88 to “0000”, RESET pin to 0V and reaches at least 1.8V within CC to “0000”, RESET pin to 0V and 193 ...

Page 194

... Give CLKI a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 – 0xFF). ATtiny48/88 194 Table 21-1 on page 191. When programming the Flash, 8008H–AVR–04/11 ...

Page 195

... Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give CLKI a positive pulse. This loads the command, and the internal write signals are reset. 8008H–AVR–04/11 ATtiny48/88 Figure 21-3 Figure 21-2 on page Figure 21-3 for signal waveforms). ...

Page 196

... WR RDY/BSY RESET +12V OE PAGEL BS2 21.2.5 Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the program data is latched into a page buffer. This allows one page of data to be ATtiny48/88 196 Figure 21-2, below. Symbols used are described in . PCMSB PAGEMSB PROGRAM PCPAGE PCWORD COUNTER ...

Page 197

... Flash” on page 194 RDY/BSY goes low 4 for signal waveforms 0x11 ADDR. HIGH ADDR. LOW DATA ATtiny48/88 for details on Command, Address and Figure 21-4, where XX means “don’t care” ADDR. LOW DATA XX XX “ ...

Page 198

... Give WR a negative pulse and wait for RDY/BSY to go high • Set BS2 to “0”. This selects low data byte EEPROM programming waveforms are illustrated in and letters refer to the programming steps described above. ATtiny48/88 198 for details on command and address loading): for details on command and data loading): ...

Page 199

... Fuse and lock bit mapping is illustrated in 8008H–AVR–04/11 Write Fuse Low byte 0x40 DATA XX 0x40 DATA Figure ATtiny48/88 Write Fuse high byte Write Extended Fuse byte 0x40 DATA XX “Programming the Flash” on page “Programming the Flash” on page 21-6, below ...

Page 200

... RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). After RESET is set low, the Programming Enable instruction needs to be executed before program/erase operations can be executed. Serial programming signals and connections are illustrated in ping is listed in ATtiny48/88 200 0 1 BS2 ...