ATxmega256A3BU Atmel Corporation, ATxmega256A3BU Datasheet
ATxmega256A3BU
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ATxmega256A3BU Summary of contents
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This document contains complete and detailed description of all modules included in ® ® ® the Atmel AVR XMEGA AU microcontroller family. The Atmel AVR XMEGA family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcon- trollers based ...
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About the Manual This document contains in-depth documentation of all peripherals and modules available for the Atme lAVR XMEGA AU microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals and ...
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Overview The AVR XMEGA AU microcontrollers is a family of low-power, high-performance, and periph- eral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel AVR XMEGA AU ...
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The Atmel AVR XMEGA AU devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 8331A–AVR–07/11 Atmel AVR XMEGA AU 4 ...
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Block Diagram Figure 2-1. Atmel AVR XMEGA AU block diagram. Digital function Oscillator / Crystal / Clock Analog function General Purpose I/O Bus masters / Programming / Debug DACA PORT A (8) ACA ADCA AREFA Int. Refs. Tempref AREFB ...
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AVR CPU 3.1 Features • 8/16-bit, high-performance Atmel AVR RISC CPU – 142 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in RAM • Stack pointer accessible in I/O memory space • Direct ...
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information ...
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Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul- tiplier supports different variations of signed and unsigned integer and fractional numbers: • Multiplication of unsigned integers • Multiplication of signed ...
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Figure 3-3 on page 9 cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 3-3. Register Operands Fetch ALU Operation Execute 3.7 Status Register The status register (SREG) ...
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The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer ...
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Figure 3-5. Bit (individually) X-register Bit (X-register) Bit (individually) Y-register Bit (Y-register) Bit (individually) Z-register Bit (Z-register) The lowest register address holds the least-significant byte (LSB), and the highest register address holds the most-significant byte (MSB). In the different addressing ...
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RAMPD Register This register is concatenated with the operand to enable direct addressing of the whole data memory space above 64KB. Together, RAMPD and the operand will form a 24-bit address. Figure 3-7. Bit (Individually) Bit (D-pointer) 3.10.3 EIND ...
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This is handled globally by the configuration change protection (CCP) register. Changes to the protected I/O registers or bits, or execution of protected instruc- tions, are only possible after the CPU writes a signature to ...
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Register Descriptions 3.14.1 CCP – Configuration Change Protection Register Bit +0x04 Read/Write Initial Value • Bit 7:0 – CCP[7:0]: Configuration Change Protection The CCP register must be written with the correct signature to enable change of the protected I/O ...
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Bit +0x09 Read/Write Initial Value • Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address bits These bits hold the MSB of the 24-bit address created by RAMPX and the 16-bit X-register. Only the number of bits required to address the available ...
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EXALL/EIJMP are used, and it will not be used if CALL and IJMP commands are used. For jump or call to addresses below 128KB, this register is not used. This register is not available if the program memory in the ...
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SREG – Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. Bit +0x0F Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable ...
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Register Summary Address Name Bit 7 +0x00 Reserved – +0x01 Reserved – +0x02 Reserved – +0x03 Reserved – +0x04 CCP +0x05 Reserved – +0x06 Reserved – +0x07 Reserved – +0x08 RAMPD +0x09 RAMPX +0x0A RAMPY +0x0B RAMPZ +0x0C EIND ...
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Memories 4.1 Features • Flash program memory – One linear address space – In-system programmable – Self-programming and boot loader support – Application section for application code – Application table section for application code or data storage – Boot ...
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This prevents unre- stricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be ...
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Application Section The Application section is the section of the flash that is used for storing the executable applica- tion code. The protection level for the application section can be selected by the boot lock bits for this section. ...
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The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be blocked). Lock bits can be written by external programmers and applica- tion software, but only to stricter protection ...
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EEPROM XMEGA AU devices ha EEPROM for nonvolatile data storage addressable in a separate data space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory mapped EEPROM ...
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Figure 4-3. 4.10.1 Bus Priority When several masters request access to the same bus, the bus priority is in the following order (from higher to lower priority): 1. Bus Master with ongoing access. 2. Bus Master with ongoing burst. a. ...
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JTAG Disable It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the device until the next device reset or until JTAG is enabled again from the application software. ...
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DATA0 – Nonvolatile Memory Data Register 0 The DATA0, DATA1, and DATA registers represent the 24-bit value DATA. This holds data dur- ing NVM read, write, and CRC access. Bit +0x04 Read/Write Initial Value • Bit 7:0 – DATA[7:0]: ...
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Bit 6:0 -CMD[6:0]: NVM Command These bits define the programming commands for the flash. Bit 6 is only set for external pro- gramming commands. See 4.15.8 CTRLA – Nonvolatile Memory Control Register A Bit +0x0B Read/Write Initial Value • ...
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Bit 0 – SPMLOCK: SPM Locked This bit can be written to prevent all further self-programming. The bit is cleared at reset, and cannot be cleared from software. This bit is protected by the configuration change protection (CCP) mechanism.Refer ...
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Bit 5:2 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 1 – EELOAD: EEPROM Page Buffer ...
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Register Descriptions – Fuses and Lockits 4.16.1 FUSEBYTE0 – Nonolatile Memory Fuse Byte 0 Bit +0x00 Read/Write Initial Value • Bit 7 – JTAGUID[7:0]: JTAG USER ID These fuses can be used to set the default JTAG user ID ...
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Bit 6 – BOOTRST: Boot Loader Section Reset Vector This fuse can be programmed so the reset vector is pointing to the first address in the boot loader flash section. The device will then start executing from the boot ...
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Bit: 4 – RSTDISBL: External Reset Disable This fuse can be programmed to disable the external reset pin functionality. When this is done pulling th pin low will not cause an external reset. A reset is required before this ...
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FUSEBYTE5 – Nonolatile Memory Fuse Byte 5 Bit +0x05 Read/Write Initial Value • Bit 7:6 – Reserved These bits are reserved. For compatibility with future devices, always write these bits to one when this register is written. • Bit ...
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LOCKBITS – Nonolatile Memory Lock Bit Register Bit +0x07 Read/Write Initial Value • Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section These lock bits control the security level for the boot loader section. The BLBB bits can ...
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Table 4-10. BLBA[1:0] • Bit 3:2 – BLBAT[1:0]: Boot Lock Bit Application Table Section These lock bits control the security level for the application table section. The BLBAT bits can only be written to a more strict locking. Resetting the ...
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Bit 1:0 – LB[1:0]: Lock Bits These lock bits control the the security level for the flash and EEPROM during external program- ming. These bits are writable only through an external programming interface. Resetting the lock bits is possible ...
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RCOSC32K – Internal 32.768kHz Oscillator Calibration Register Bit +0x02 Read/Write Initial Value • Bit 7:0 – RCOSC32K[7:0]: Internal 32.768kHz Oscillator Calibration Value This byte contains the oscillator calibration value for the internal 32.768kHz oscillator. Calibra- tion of the oscillator ...
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LOTNUM0 – Lot Number Register 0 LOTNUM0, LOTNUM1, LOTNUM2, LOTNUM3, LOTNUM4 and LOTNUM5 contain the lot num- ber for each device. Together with the wafer number and wafer coordinates this gives a serial number for the device. Bit +0x08 ...
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LOTNUM4 – Lot Number Register 4 Bit +0x0C Read/Write Initial Value • Bit 7:0 – LOTNUM4[7:0]: Lot Number Byte 4 This byte contains byte 4 of the lot number for the device. 4.17.11 LOTNUM5 – Lot Number Register 5 ...
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COORDX1 – Wafer Coordinate X Register 1 Bit +0x13 Read/Write Initial Value • Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 1 This byte contains byte 1 of wafer coordinate X for the device. 4.17.15 COORDY0 – Wafer Coordinate ...
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USBCAL1 – USB Pad Calibration Register 1 Bit +0x1B Read/Write Initial Value • Bit 7:0 – USBCAL1[7:0]: USB Pad Calibration Register 1 This byte contains byte 1 of the USB pin calibration data, and must be loaded into the ...
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Bit 7:0 – ADCACAL1[7:0]: ADCA Calibration Byte 1 This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA CALH register. 4.17.22 ADCBCAL0 – ADCB Calibration Register 0 ADCBCAL0 and ADCBCAL1 contains the ...
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TEMPSENSE1 – Temperature Sensor Calibration Register 1 Bit +0x2F Read/Write Initial Value • Bit 7:0 – TEMPSENSE1[7:0]: Temperature Sensor Calibration Byte 1 This byte contains byte 1 of the temperature measurement. 4.17.26 DACA0OFFCAL – DACA Offset Calibration Register Bit ...
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Bit 7:0 – DACB0OFFCAL[7:0]: DACB0 Offset Calibration Byte This byte contains the offset calibration value for channel 0 in the digitaltoanalog converter B (DACB). Calibration is done during production test of the device. The calibration byte is not loaded ...
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DACB1OFFCAL – DACB Offset Calibration Register Bit +0x33 Read/Write Initial Value • Bit 7:0 – DACB1OFFCAL[7:0]: DACB1 Offset Calibration Byte This byte contains the offset calibration value for channel 1 in the digitaltoanalog converter B (DACB). Calibration is done ...
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Register Descriptions – MCU Control 4.20.1 DEVID0 – MCU Device ID Register 0 DEVID0, DEVID1 and DEVID2 contain the -byte identification that identif each microcontroller device type. For details on the actual ID, refer to the device datasheet. Bit ...
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Bit 3:0 – REVID[3:0]: MCU Revision ID These bits contains the device revision and so on. 4.20.5 JTAGUID – JTAG User ID Register Bit +0x04 Read/Write Initial Value • Bit 7:0 – JTAGUID[7:0]: JTAG ...
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This reduces the peak current consumption during startup of the module. For maximum effect the start-up delay should be set so that it is larger than 0.5µs. Table 4-13. STARTUPDLYx 4.20.8 EVSYSLOCK – Event System Lock Register ...
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Bit 7:3 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 2 – AWEXELOCK: Advanced Waveform Extension ...
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Register Summary - NVM Controller Address Name Bit 7 +0x00 ADDR0 +0x01 ADDR1 +0x02 ADDR2 +0x03 Reserved – +0x04 DATA0 +0x05 DATA1 +0x06 DATA2 +0x07 Reserved – +0x08 Reserved – +0x09 Reserved – +0x0A CMD – +0x0B CTRLA – ...
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Register Summary - Production Signature Row Address Auto Load Name +0x00 YES RCOSC2M +0x01 YES RCOSC2MA +0x02 YES RCOSC32K +0x03 YES RCOSC32M +0x04 YES RCOSC32MA +0x05 Reserved +0x06 Reserved +0x07 Reserved +0x08 NO LOTNUM0 +0x09 NO LOTNUM1 +0x0A NO ...
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Register Summary - General Purpose I/O Registers Address Name Bit 7 +0x00 GPIOR0 +0x01 GPIOR1 +0x02 GPIOR2 +0x03 GPIOR3 +0x04 GPIOR4 +0x05 GPIOR5 +0x06 GPIOR6 +0x07 GPIOR7 +0x08 GPIOR8 +0x09 GPIOR9 +0x0A GPIOR10 +0x0B GPIOR11 +0x0C GPIOR12 +0x0D GPIOR13 ...
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DMAC - Direct Memory Access Controller 5.1 Features • Allows high speed data transfers with minimal CPU intervention – from data memory to data memory – from data memory to peripheral – from peripheral to data memory – from ...
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To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa. 5.3 DMA Transaction A complete DMA read and write operation between memories and/or peripherals ...
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For a list of all transfer triggers, refer to page 63. By default, a trigger starts a block transfer operation. When the block transfer is complete, the channel is automatically disabled. When enabled again, the channel will wait for ...
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Transfer Buffers To avoid unnecessary bus loading when doing data transfer between memories with different access timing (for example, I/O register and external memory), the DMA controller has a four- byte buffer. Two bytes will be read from the ...
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Register Description – DMA Controller 5.13.1 CTRL – DMA Control Register Bit +0x00 Read/Write Initial Value • Bit 7 – ENABLE: DMA Enable Setting this bit enables the DMA controller. If the DMA controller is enabled and this bit ...
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INTFLAGS – DMA Interrupt Status Register Bit +0x03 Read/Write Initial Value • Bit 7:4 – CHnERRIF[3:0]: DMA Channel n Error Interrupt Flag If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing ...
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TEMPH – DMA Temporary Register High Bit +0x07 Read/Write Initial Value • Bit 7:0 – TEMP[15:8]: DMA Temporary Register This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of the 24-bit register ...
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Bit 2 – SINGLE: DMA Channel Single-Shot Data transfer Setting this bit enables the single-shot mode. The channel will then do a burst transfer of BURSTLEN bytes on the transfer trigger. A write to this bit will be ignored ...
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CTRLB – DMA Channel Control Register B Bit +0x04 Read/Write Initial Value • Bit 7 – CHBUSY - DMA Channel Busy When the DMA channel starts a DMA transaction, the CHBUSY flag will be read as one. This flag ...
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Bit 7:6 – SRCRELOAD[1:0]: DMA Channel Source Address Reload These bits decide the DMA channel source address reload according to these bits is ignored while the channel is busy. Table 5-5. SRCRELOAD[1:0] • Bit 5:4 – SRCDIR[1:0]: DMA Channel ...
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Table 5-8. DESTDIR[1:0] 5.14.4 TRIGSRC – DMA Channel Trigger Source Bit +0x03 Read/Write Initial Value • Bit 7:0 – TRIGSRC[7:0]: DMA Channel Trigger Source Select These bits select which trigger source is used for triggering a transfer on the DMA ...
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Table 5-9. TRIGSRC Base Value Table 5-10. TRGSRC Offset Value Table 5-11. TRGSRC offset value Notes: 8331A–AVR–07/11 DMA trigger source base values for all modules and peripherals. (Continued) Group Configuration 0x60 TCD0 0x66 TCD1 0x6A SPID 0x6B USARTD0 0x6E USARTD1 ...
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Table 5-12. TRGSRC Offset Value Note: Table 5-13. TRGSRC Offset Value The group configuration is the “base_offset;” for example, TCC1_CCA for the timer/counter C1 CC channel A the transfer trigger. 5.14.5 TRFCNTL – DMA Channel Block Transfer Count Register L ...
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Bit 7:0 – TRFCNT[15:8]: DMA Channel n Block Transfer Count Register High byte These bits hold the MSB of the 16-bit block transfer count. The default value of this register is 0x1 user writes 0x0 to this ...
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SRCADDR2 – DMA Channel Source Address 2 Reading and writing 24-bit values require special attention. For details, refer to and 32-bit Registers” on page Bit +0x0A Read/Write Initial Value • Bit 7:0 – SRCADDR[23:16]: DMA Channel Source Address 2 ...
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Register Summary – DMA Controller Address Name Bit 7 +0x00 CTRL ENABLE +0x01 Reserved – +0x02 Reserved – +0x03 INTFLAGS CH3ERRIF +0x04 STATUS CH3BUSY +0x05 Reserved – +0x06 TEMPL +0x07 TEMPH +0x10 CH0 Offset +0x20 CH1 Offset +0x30 CH2 ...
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Event System 6.1 Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events – CPU and DMA controller independent operation – 100% predictable signal timing – Short and guaranteed ...
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Figure 6-1. The event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to eight parallel event configurations and routings. The maximum routing latency is ...
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Figure 6-2. Events can also be generated manually in software. 6.3.1 Signaling Events Signaling events are the most basic type of event. A signaling event does not contain any infor- mation apart from the indication of a change in a ...
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Software-generated events last for one clock cycle and will overwrite events from other event generators on that event channel during that clock cycle. Table 6-1 on page 72 they are decoded. Table 6-1. STROBE 6.4 Event ...
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Figure 6-3. Eight multiplexers means that it is possible to route up to eight events at the same time also possible to route one event through several multiplexers. Not all XMEGA devices contain all peripherals. This only means ...
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Event Timing An event normally lasts for one peripheral clock cycle, but some event sources, such as a low level on an I/O pin, will generate events continuously. Details on this are described in the datasheet for each peripheral, ...
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Figure 6-4. Figure 6-4 QDPH90 are the two quadrature signals. When QDPH90 leads QDPH0, the rotation is defined as positive or forward. When QDPH0 leads QDPH90, the rotation is defined as negative or reverse. The concatenation of the two phase ...
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Set the period register of the timer/counter to ('line count 1), the line count of the quadrature encoder. • Enable the timer/counter without clock prescaling. The angle of a quadrature encoder attached to QDPH0, QDPH90 (and ...
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Table 6-3. CHnMUX[7:4] 0001 0001 0001 0001 0010 0010 0010 0011 0100 0101 0101 0110 0110 0111 0111 1000 1001 1010 1011 1100 1100 1101 1101 1110 1110 1111 1111 Notes: Table 6-4. T/C Event ...
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Table 6-4. T/C Event 6.8.2 CHnCTRL – Event Channel n Control Register Bit Read/Write Initial Value • Bit 7 – Reserved This bit is reserved and will always be read as zero. For compatibility with future ...
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Table 6-6. DIGFILT[2:0] 6.8.3 STROBE – Event Strobe Register If the STROBE register location is written, each event channel will be set according to the STROBE[n] and corresponding DATA[n] bit settings, if any are unequal to zero. A single event ...
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Register Summary Address Name Bit 7 +0x00 CH0MUX +0x01 CH1MUX +0x02 CH2MUX +0x03 CH3MUX +0x04 CH4MUX +0x05 CH5MUX +0x06 CH6MUX +0x07 CH7MUX +0x08 CH0CTRL – +0x09 CH1CTRL – +0x0A CH2CTRL – +0x0B CH3CTRL – +0x0C CH4CTRL – +0x0D CH5CTRL ...
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System Clock and Clock Options 7.1 Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: – 32MHz run-time calibrated oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) ...
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Figure 7-1. The clock system, clock sources, and clock distribution. Real Time Counter Brown-out Watchdog Detector Timer 32 kHz Int. ULP 8331A–AVR–07/11 Peripherals clk PER clk PER2 clk PER4 clk RTC RTCSRC XOSCSEL 32.768 kHz 32.768 kHz 0.4 – 16 ...
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Clock Distribution Figure 7-1 on page 82 7.3.1 System Clock - Clk SYS The system clock is the output from the main system clock selection. This is fed into the prescal- ers that are used to generate all internal ...
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Calibrated Oscillator This oscillator provides an approximate 32.768kHz clock calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the ...
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Figure 7-3. 7.4.2.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A typical connection is shown in ure 7-4 on page oscillator can ...
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Figure 7-5. System clock selection and prescalers. Clock Selection Internal 32.768kHz Osc. Internal 2MHz Osc. Internal 32MHz Osc. Clk SYS Internal PLL. External Oscillator or Clock. Prescaler A divides the system clock, and the resulting clock is clk be enabled ...
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DFLL 2MHz and DFLL 32MHz Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the 2MHz and 32MHz internal oscillators. The DFLL compares the oscillator frequency with a more accurate reference clock to ...
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The value that should be written to the COMP register is given by the following formula: When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the internal oscillator runs too ...
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Issue a non-maskable interrupt (NMI) If the PLL or external clock source fails when not being used for the system clock automati- cally disabled, and the system clock will continue to operate normally. No NMI is issued. ...
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Register Description - Clock 7.9.1 CTRL – System Clock Control Register Bit +0x00 Read/Write Initial Value • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits ...
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Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor These bits define the division ratio of the clock prescaler A according to can be written at run-time to change the frequency of the Clk clock, Clk Table 7-2. PSADIV[4:0] • ...
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LOCK – Clock System Lock Register Bit +0x02 Read/Write Initial Value • Bit 7:1 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when ...
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Bit 0 – RTCEN: RTC Clock Source Enable Setting the RTCEN bit enables the selected RTC clock source for the real-time counter. 7.9.5 USBSCTRL – USB Control Register Bit +0x04 Read/Write Initial Value • Bit 7:6 – Reserved These ...
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Register Description — Oscillator 7.10.1 CTRL – Oscillator Control Register Bit +0x00 Read/Write Initial Value • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to ...
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STATUS – Oscillator Status Register Bit +0x01 Read/Write Initial Value • Bit 7:5 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this ...
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Table 7-7. FRQRANGE[1:0] • Bit 5 – X32KLPM: Crystal Oscillator 32.768kHz Low Power Mode Setting this bit enables the low power mode for the 32.768kHz crystal oscillator. This will reduce the swing on the TOSC2 pin. • Bit 4 – ...
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XOSCFAIL – XOSC Failure Detection Register Bit +0x03 Read/Write Initial Value • Bit 7:4 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when ...
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PLLCTRL – PLL Control Register Bit +0x05 Read/Write Initial Value • Bit 7:6 – PLLSRC[1:0]: Clock Source The PLLSRC bits select the input source for the PLL according to Table 7-9. PLLSRC[1:0] Notes: • Bit 5 – PLLDIV: PLL ...
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Table 7-10. RC32MCREF[1:0] • Bit 0 – RC2MCREF: 2MHz Oscillator Calibration Reference This bit is used to select the calibration source for the ...
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Bit 7 – Reserved This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 6:0 – CALA[6:0]: DFLL Calibration Bits ...
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COMP2 – DFLL Compare Resgister Byte 2 Bit +0x06 Read/Write Initial Value • Bit 7:0 – COMP2[15:8]: Compare Register Byte 2 These bits hold byte 2 of the 16-bit compare register. Table 7-11. 8331A–AVR–07/ COMP[15:8] ...
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Register Summary - Clock Address Name Bit 7 +0x00 CTRL – +0x01 PSCTRL – +0x02 LOCK – +0x03 RTCCTRL – +0x04 USBSCTRL – +0x05 Reserved – +0x06 Reserved – +0x07 Reserved – 7.13 Register Summary - Oscillator Address Name ...
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Power Management and Sleep Modes 8.1 Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable ...
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Table 8-1 on page 104 tors, and wake-up sources. Table 8-1. Sleep Modes Idle Power down Power save Standby Extended standby The wake-up time for the device is dependent on the sleep mode and the main clock source. The startup ...
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Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 8.3.5 Extended Standby Mode ...
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Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and, hence, always consume power. Refer to ...
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Register Description – Sleep 8.6.1 CTRL – Sleep Control Register Bit +0x00 Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to ...
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Bit 7 – Reserved This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 6 – USB: USB Module Setting ...
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Bit 1 – ADC: Power Reduction ADC Setting this bit stops the clock to the ADC. The ADC should be disabled before stopped. • Bit 0 – AC: Power Reduction Analog Comparator Setting this bit stops the clock to ...
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Register Summary - Sleep Address Name Bit 7 +0x00 CTRL – 8.9 Register Summary - Power Reduction Address Name Bit 7 +0x00 PRGEN – +0x01 PRPA – +0x02 PRPB – +0x03 PRPC – +0x04 PRPD – +0x05 PRPE – ...
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Reset System 9.1 Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset – Brownout ...
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Figure 9-1. 9.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through ...
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Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is chosen as the source for Clk 9.3.2 Oscillator Startup After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values ...
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When the BOD is enabled and V 9-4), the brownout reset is immediately activated. When V MCU after the timeout period, t The trigger level has a hysteresis to ensure spike free brownout detection. The hysteresis on the detection level ...
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Enabled: In this mode, the V for a period of t • Sampled: In this mode, the BOD circuit will sample the V that of the 1kHz output from the ultra low power (ULP) internal oscillator. Between each sample, ...
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Figure 9-6. For information on configuration and use of the WDT, refer to the page 126. 9.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the soft- ware reset bit ...
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Register Description 9.5.1 STATUS – Reset Status Register Bit +0x00 Read/Write Initial Value • Bit 7:6 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to ...
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Register Summary Address Name Bit 7 +0x00 STATUS – +0x01 CTRL – 8331A–AVR–07/11 Bit 6 Bit 5 Bit 4 Bit 3 – SRF PDIRF WDRF – – – Atmel AVR XMEGA AU Bit 2 Bit 1 Bit 0 BORF ...
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Battery Backup System 10.1 Features • Integrated battery backup system ensuring continuos, real-time clock during main power failure • Battery backup power supply from dedicated V – One 32-bit real-time counter – One ultra low power 32.768kHz crystal oscillator ...
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Battery Backup System The battery backup system consists lator with failure monitor, a 32-bit real-time counter (RTC), and two backup registers. Figure 10-1. Battery backup system and its power domain implementation. VBAT TOSC1 TOSC2 10.3.1 Power ...
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Crystal Oscillator with Failure Monitor The crystal oscillator (XOSC) supports connection of a external 32.768kHz crystal. It provides a prescaled clock output selectable to 1.024kHz or 1Hz. The crystal oscillator is designed for ultra low power consumption and by ...
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Main Power Restore and Start-up Sequence At every startup after main power is restored, the software should: 1. Control the main reset source to determine that a POR or BOD took place. 2. Check for power on the V ...
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Register Description 10.6.1 CTRL: Control Register Bit +0x00 Read/Write initial Value • Bit 7: 6 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this ...
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This bit is protected by the Configuration Change Protection mechanism. For a detailed descrip- tion, refer to 10.6.2 STATUS: Status Register Bit +0x01 Read/Write Initial Value • Bit 7 – BBPWR: Battery Backup Power This flag is set if no ...
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Bit 7:0 – BACKUP0[7:0]: Backup Register 0 This register can be used to store data in the battery backup system before the main power is lost or removed. 10.6.4 BACKUP1: Battery Backup Register 1 Bit +0x03 Read/Write Initial Value ...
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WDT – Watchdog Timer 11.1 Features • Issues a device reset if the timer is not reset before its timeout period • Asynchronous operation from dedicated oscillator • 1kHz output of the 32kHz ultra low power oscillator • 11 ...
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Figure 11-1. Normal mode operation. 11.4 Window Mode Operation In window mode operation, the WDT uses two different timeout periods, a "closed" window time- out period (TO defines a duration of from 8ms to 8s where the WDT cannot be ...
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Configuration Protection and Lock The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT settings. The first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing the WDT control ...
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Table 11-1. PER[3:0] 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 • Bit 1 – ENABLE: Watchdog Enable This bit enables the WDT. Clearing this bit disables the watchdog timer. In order to change this bit, the CEN ...
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The initial values of these bits are set by the watchdog window timeout period (WDWP) fuses, and are loaded at power-on. In normal mode these bits are not in use. In order to change these bits, the WCEN bit must ...
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Bit 7:1 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 0 – SYNCBUSY When writing to ...
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Interrupts and Programmable Multilevel Interrupt Controller 12.1 Features • Short and predictable interrupt response time • Separate interrupt configuration and vector address for each interrupt • Programmable multilevel interrupt controller – Interrupt prioritizing according to level and vector address ...
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The PMIC status register contains state information that ensures that the PMIC returns to the correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an interrupt handler. Returning from an interrupt will return the ...
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If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is served. See Figure 12-1. Interrupt execution of a multicycle instruction interrupt occurs when the device is in sleep mode, the ...
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Interrupt level The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre- sponding bit values for the interrupt level ...
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Figure 12-2. Static priority. 12.6.2 Round-robin Scheduling To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be served, the PMIC offers round-robin scheduling for low-level interrupts. When round-robin scheduling is enabled, the ...
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Moving Interrupts Between Application and Boot Sections The interrupt vectors can be moved from the default location in the application section in flash to the start of the boot section. 12.8 Register Description 12.8.1 STATUS – PMIC Status Register ...
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This register is not reinitialized to its initial value if round-robing scheduling is disabled, and so if default static priority is needed, the register must be written to zero. 12.8.3 CTRL – PMIC Control Register ...
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I/O Ports 13.1 Features • General purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: – Totem-pole – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O • Input with synchronous and/or ...
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Figure 13-1 on page 140 controlling a pin. Figure 13-1. General I/O pin functionality. 13.3 I/O Pin Use and Configuration Each port has one data direction (DIR) register and one data output value (OUT) register that are used for port ...
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The pin n configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole, wired-AND, or wired-OR configuration also possible to enable inverted input and output for a pin. A totem-pole ...
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Totem-pole with Pull-up In this mode, the configuration is as for totem-pole, expect the pin is configured with internal pull- up when set as input. Figure 13-4. I/O pin configuration - Totem-pole with pull-up (on input). 13.3.2 Bus-keeper In ...
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Figure 13-6. Output configuration - Wired-OR with optional pull-down. 13.3.4 Wired-AND In the wired-AND configuration, the pin will be driven low when the corresponding bits in the OUT and DIR registers are written to zero. When the OUT register is ...
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Figure 13-8. Synchronization when reading a pin value. SYNCHRONIZER FLIPFLOP 13.5 Input Sense Configuration Input sensing is used to detect an edge or level on the I/O pin input. The different sense configu- rations that are available for each pin ...
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Port Interrupt Each port has two interrupt vectors, and it is configurable which pins on the port will trigger each interrupt. Port interrupts must be enabled before they can be used. Which sense configurations can be used to generate ...
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Table 13-3. Sense Settings Rising edge Falling edge Both edges Low level 13.7 Port Event Port pins can generate an event when there is a change on the pin. The sense configurations decide the conditions for each pin to generate ...
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Figure 13-10. Port override signals and related logic. 13.9 Slew Rate Control Slew rate control can be enabled for all I/O pins individually. Enabling the slew rate limiter will typically increase the rise/fall time by 50% to 150%, depending on ...
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Multi-pin configuration The multi-pin configuration function is used to configure multiple port pins using a single write operation to only one of the port pin configuration registers. A mask register decides which port pin is configured when one port ...
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Register Descriptions – Ports 13.13.1 DIR – Data Direction Register Bit +0x00 Read/Write Initial Value • Bit 7:0 – DIR[7:0]: Data Direction This register sets the data direction for the individual pins of the port. If DIRn is written ...
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Bit 7:0 – DIRTGL[7:0]: Port Data Direction Toggle This register can be used instead of a read-modify-write to toggle the direction of individual pins. Writing a one to a bit will toggle the corresponding bit in the DIR register. ...
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OUTTGL – Data Output Value Toggle Register Bit +0x07 Read/Write Initial Value • Bit 7:0 – OUTTGL[7:0]: Port Data Output Value Toggle This register can be used instead of a read-modify-write to toggle the output value of individual pins. ...
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Bit 7:0 – INT0MSK[7:0]: Interrupt 0 Mask Register These bits are used to mask which pins can be used as sources for port interrupt 0. If INT0MASKn is written to one, pin n is used as source for port ...
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Bit 4 – USART0: USART0 Remap Setting this bit to one will move the pin location of USART0 from Px[3:0] to Px[7:4]. • Bit 3 – TC0D: Timer/Counter 0 Output Compare D Setting this bit will move the location ...
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Table 13-4. OPC[2:0] 000 001 010 011 100 101 110 111 • Bit 2:0 – ISC[2:0]: Input/Sense Configuration These bits set the input and sense configuration on pin n according to configuration decides how the pin can trigger port interrupts ...
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Register Descriptions – Port Configuration 13.14.1 MPCMASK – Multi-pin Configuration Mask Register Bit +0x00 Read/Write Initial Value • Bit 7:0 – MPCMASK[7:0]: Multi-pin Configuration Mask The MPCMASK register enables configuration of several pins of a port at the same ...
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Bit 3:0 – VP2MAP: Virtual Port 2 Mapping These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN, and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing ...
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Table 13-7 on page 157 Table 13-7. EVOUT[1:0] • Bits 3:2 – CLKOUTSEL[1:0] : Clock Output Select These bits are used to select which of the peripheral clocks will be output to the port pin if CLK- OUT is configured. ...
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Bit 3:2 – EBIADROUT[1:0]: EBI Address Output The maximum configuration of the external bus interface (EBI) requires dedicated pins. For devices with only 24 EBI pins available, eight additional pins can be enabled and placed on ...
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Bit 2:0 – EVOUTSEL[2:0]: Event Channel Output Selection These bits define which channel from the event system is output to the port pin. page 159 Table 13-13. Event channel output selection. EVOUTSEL[2:0] 8331A–AVR–07/11 shows the available selections. Group Configuration ...
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Register Descriptions – Virtual Port 13.15.1 DIR - Data Direction Bit +0x00 Read/Write Initial Value • Bit 7:0 – DIR[7:0]: Data Direction Register This register sets the data direction for the individual pins in the port mapped by VPCTRLA, ...
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INTFLAGS – Interrupt Flag Register Bit +0x03 Read/Write Initial Value • Bit 7:2 – Reserved These bits are reserved and will always be read as zero. For compatibility with future devices, always write these bits to zero when this ...
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Register Summary – Ports Address Name Bit 7 +0x00 DIR +0x01 DIRSET +0x02 DIRCLR +0x03 DIRTGL +0x04 OUT +0x05 OUTSET +0x06 OUTCLR +0x07 OUTTGL +0x08 IN +0x09 INTCTRL – +0x0A INT0MASK +0x0B INT1MASK +0x0C INTFLAGS – +0x0D Reserved – ...
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Interrupt Vector Summary - Ports Table 13-14. Port interrupt vectors and their word offset address. Offset Source 0x00 INT0_vect 0x02 INT1_vect 8331A–AVR–07/11 Interrupt Description Port interrupt vector 0 offset Port interrupt vector 1 offset Atmel AVR XMEGA AU 163 ...
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TC0/1 - 16-bit Timer/Counter Type 0 and 1 14.1 Features • 16-bit timer/counter • 32-bit timer/counter support by cascading two timer/counters • four compare or capture (CC) channels – Four CC channels for timer/counters of type 0 ...
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There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only ...
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When used for capture operations, the CC channels are referred to as “capture channels.” 14.3 Block Diagram Figure 14-2 on page 166 extensions. Figure 14-2. Timer/counter block diagram. Bus Bridge The counter register (CNT), period registers with buffer ...
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The waveform generator modes use these comparisons to set the waveform period or pulse width. A prescaled peripheral clock and events from the event system can be used to control the coun- ter. The event system is also used as ...
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UPDATE condition. This is shown for a compare register in Figure 14-4 on page Figure 14-4. Period and compare double buffering UPDATE When the CC channels are used for a capture operation, a similar ...
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Normal Operation In normal operation, the counter will count in the direction set by the direction (DIR) bit for each clock until it reaches TOP or BOTTOM. When up-counting and TOP is reached, the counter will be set to ...
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Figure 14-7. Changing the period without buffering. CNT A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in and if a new TOP value that is lower than current CNT is written to ...
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Capture Channel The CC channels can be used as capture channels to capture external events and give them a timestamp. To use capture, the counter must be set for normal operation. Events are used to trigger the capture; i.e., ...
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Figure 14-11. Input capture timing. CNT 14.7.2 Frequency Capture Selecting the frequency capture event action makes the enabled capture channel perform an input capture and restart on positive edge events. This enables the timer/counter to measure the period or frequency ...
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Pulse Width Capture Selecting the pulse width measure event action makes the enabled compare channel perform the input capture action on falling edge events and the restart action on rising edge events. The counter will then restart on positive ...
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Waveform Generation The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform visible on the connected port pin, the following ...
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TOP and then restarts from BOTTOM. The waveform generator (WG) output is set on the compare match between the CNT and CCx registers and cleared at TOP. Figure 14-15. Single-slope pulse width modulation. CNT WG Output The PER register ...
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Figure 14-16. Dual-slope pulse width modulation. CNT WG Output Using dual-slope PWM results in a lower maximum operation frequency compared to the single- slope PWM operation. The period register (PER) defines the PWM resolution. The minimum resolution is 2 bits ...
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Figure 14-17. Port override for timer/counter 0 and 1. 14.9 Interrupts and events The timer/counter can generate both interrupts and events. The counter can generate an inter- rupt on overflow/underflow, and each CC channel has a separate interrupt that is ...
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Register Description 14.12.1 CTRLA – Control Register A Bit +0x00 Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when ...
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Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode These bits ...
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CTRLD – Control Register D Bit +0x03 Read/Write Initial Value • Bit 7:5 – EVACT[2:0]: Event Action These bits define the event action the timer will perform on an event according to page 180. The EVSEL setting will decide ...
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Table 14-6. EVSEL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1nnn 14.12.5 CTRLE – Control Register E Bit +0x04 Read/Write Initial Value • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with ...
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Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level These bits ...
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Bit 3:2 – CMD[1:0]: Command These bits can be used for software control of update, restart, and reset of the timer/counter. The command bits are always read as zero. Table 14-8. CMD • Bit 1 ...
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INTFLAGS – Interrupt Flag Register Bit +0x0C Read/Write Initial Value • Bit 7:4 – CCxIF: Compare or Capture Channel x Interrupt Flag The compare or capture interrupt flag (CCxIF) is set on a compare match input ...
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For more details, refer to Bit +0x0F Read/Write Initial Value 14.12.12 CNTL – Counter Register L The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT contains the 16-bit counter value in the timer/counter. CPU and DMA write ...
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PERH – Period Register H Bit +0x27 Read/Write Initial Value • Bit 7:0 – PER[15:8] These bits hold the MSB of the 16-bit period register. 14.12.16 CCxL – Compare or Capture x Register L The CCxH and CCxL register ...
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Bit 7:0 – PERBUF[7:0] These bits hold the LSB of the 16-bit period buffer register. 14.12.19 PERBUFH – Timer/Counter Period Buffer H Bit +0x37 Read/Write Initial Value • Bit 7:0 – PERBUF[15:8] These bits hold the MSB of the ...
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Register Summary Address Name Bit 7 +0x00 CTRLA – +0x01 CTRLB CCDEN +0x02 CTRLC – +0x03 CTRLD +0x04 CTRLE – +0x05 Reserved – +0x06 INTCTRLA – +0x07 INTCTRLB CCCINTLVL[1:0] +0x08 CTRLFCLR – +0x09 CTRLFSET – +0x0A CTRLGCLR – +0x0B ...
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TC2 –16-bit Timer/Counter type 2 15.1 Features • A system of two 8-bit Timer/Counters – Low Byte Timer/Counter – High Byte Timer/Counter • 8 Compare Channels – 4 Compare Channels for the Low Byte Timer/Counter – 4 Compare Channels ...
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Block Diagram Figure 15-1. 16-bit Timer/Counter0 with Split Mode Block Diagraml 15.4 Clock Sources The Timer/Counter can be clocked from the Peripheral Clock (clk tem. Figure 15-2 8331A–AVR–07/11 Base Counter HPER LPER Counter HCNT LCNT = ...
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Figure 15-2. Clock Selection clk PER The Peripheral Clock (clk in a device). A selection of the prescaler outputs from 1 to 1/2024 is directly available. In addition the whole range from The clock selection (CLKSEL) selects ...
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Figure 15-4. Changing the period CNT 15.6 Compare Channel Each compare channel continuously compares the counter value with the CMPx register. If CNT equals CMPx the comparator signals a match. For the Low Byte Timer/Counter the match will set the ...
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Figure 15-5. Single slope Pulse Width Modulation CNT WG Output The PER register defines the PWM resolution. The minimum resolution is 2-bit (PER=0x0003), and the maximum resolution is 8-bit (PER=MAX). The following equation is used to calculate the exact resolution ...
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Interrupts and events The T/C can generate both interrupts and events. The Counter can generate an interrupt on underflow, and each CMP channel for Counter A has a separate interrupt that is used for compare. Event will be generated ...
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Register Description 15.10.1 CTRLA — Control Register A Bit +0x00 Read/Write Initial Value • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when ...
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CTRLC — Control Register C Bit +0x02 Read/Write Initial Value • Bit 7:0 – CMPHx/CMPLx: Compare Output Value High/Low x These bits allow direct access to the Waveform Generator's output compare value when the Timer/Counter is OFF. This is ...
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Bit 3:2 – UNFHINTLVL[1:0]: High Byte Timer Underflow Interrupt Level These bits enable the High Byte Timer Underflow Interrupt and select the interrupt level as described in enabled interrupt will be triggered when the UNFHIF in the INTFLAGS register ...
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Bit 1:0 – CMDEN[1:0]: Command Enable These bits are used to indicate for which Timer/Counter the command (CMD) is valid. Table 15-5. CMD 15.10.8 INTFLAGS — Interrupt Flag Register Bit +0x0C Read/Write Initial Value • ...
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CNTH – Count Register High Bit +0x21 Read/Write Initial Value • Bit 7:0 – CNTH[7:0] CNTH contains the 8-bit counter value for the High Byte Timer/Counter. The CPU and DMA write access has priority over count, clear, or reload ...
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CMPHx – High Byte Compare Register x Bit Read/Write Initial Value • Bit 7:0 – CMPHx[7:0], x=[ CMPHx contains the 8-bit Compare value for the High Byte Timer/Counter. These registers are all continuously compared to the ...