SAM3U4E Atmel Corporation, SAM3U4E Datasheet
SAM3U4E
Specifications of SAM3U4E
Related parts for SAM3U4E
SAM3U4E Summary of contents
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Features • Core ® ® – ARM Cortex -M3 revision 2.0 running MHz – Memory Protection Unit (MPU) ® – Thumb -2 instruction set • Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide ...
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... SDIO, USB to SPI, USB to External Bus Interface). 1.1 Configuration Summary The SAM3U series differ in memory sizes, package and features list. configurations of the six devices. Table 1-1. Configuration Summary Flash Device Flash Organization SRAM 2x128 52 SAM3U4E dual plane Kbytes Kbytes 128 36 SAM3U2E single plane Kbytes Kbytes 64 20 SAM3U1E ...
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SAM3U Block Diagram Figure 2-1. 144-pin SAM3U4/2/1E Block Diagram MASTER SLAVE System Controller JTAG & Serial Wire TST PCK0 -PCK2 In-Circuit Emulator PLLA SysTick Counter UPLL Cortex-M3 Processor PMC Fmax 96 MHz OSC XIN 3-20 M XOUT MPU RC ...
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Figure 2-2. 100-pin SAM3U4/2/1C Block Diagram MASTER SLAVE System Controller JTAG & Serial Wire TST PCK0 -PCK2 In-Circuit Emulator PLLA SysTick Counter UPLL Cortex-M3 Processor PMC Fmax 96 MHz OSC XIN XOUT 3-20 M MPU RC Osc. I/D 12/8/4 M ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIO Peripherals I/O Lines Power Supply VDDIN Voltage Regulator Input VDDOUT Voltage Regulator Output VDDUTMII USB UTMI+ Interface Power Supply GNDUTMII USB UTMI+ Interface Ground VDDBU Backup ...
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Table 3-1. Signal Description List (Continued) Signal Name Function ERASE Flash and NVM Configuration Bits Erase Command NRST Microcontroller Reset NRSTB Asynchronous Microcontroller Reset TST Test Select URXD UART Receive Data UTXD UART Transmit Data PA0 - PA31 Parallel IO ...
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Table 3-1. Signal Description List (Continued) Signal Name Function CK Multimedia Card Clock CDA Multimedia Card Slot A Command DA0 - DA7 Multimedia Card Slot A Data Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock TXDx USARTx ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWDx TWIx Two-wire Serial Data TWCKx TWIx Two-wire Serial Clock AD12Bx Analog Inputs AD12BTRG ADC Trigger AD12BVREF ADC Reference ADx Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling ...
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Package and Pinout The SAM3U4/2/1E is available in 144-lead LQFP and 144-ball LFBGA packages. The SAM3U4/2/1C is available in 100-lead LQFP and 100-ball LFBGA packages. 4.1 SAM3U4/2/1E Package and Pinout 4.1.1 144-ball LFBGA Package Outline The 144-Ball LFBGA package ...
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LQFP Pinout Table 4-1. 144-pin SAM3U4/2/1E Pinout 1 TDI 37 2 VDDOUT 38 3 VDDIN 39 4 TDO/TRACESWO 40 5 PB31 41 6 PB30 42 7 TMS/SWDIO 43 8 PB29 44 9 TCK/SWCLK 45 10 PB28 46 11 ...
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LFBGA Pinout Table 4-2. 144-ball SAM3U4/2/1E Pinout A1 VBG A2 VDDUTMI A3 PB9 A4 PB10 A5 PB19 A6 PC21 A7 PB26 A8 TCK/SWCLK A9 PB30 A10 TDO/TRACESWO A11 XIN32 A12 XOUT32 B1 VDDCORE B2 GNDUTMI B3 XOUT B4 ...
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SAM3U4/2/1C Package and Pinout 4.2.1 100-lead LQFP Package Outline Figure 4-3. 4.2.2 100-ball LFBGA Package Outline Figure 4-4. SAM3U Series 12 Orientation of the 100-lead LQFP Package 75 76 100 1 Orientation of the 100-ball LFBGA Package TOP VIEW ...
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LQFP Pinout Table 4-3. 100-pin SAM3U4/2/1C1 Pinout 1 VDDANA 2 ADVREF 3 GNDANA 4 AD12BVREF 5 PA22/PGMD14 6 PA30 7 PB3 8 PB4 9 VDDCORE 10 PA13/PGMD5 11 PA14/PGMD6 12 PA15/PGMD7 13 PA16/PGMD8 14 PA17/PGMD9 15 PB16 16 ...
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LFBGA Pinout Table 4-4. 100-ball SAM3U4/2/1C Pinout A1 VBG C6 A2 XIN C7 A3 XOUT C8 A4 PB17 C9 A5 PB21 C10 A6 PB23 D1 A7 TCK/SWCLK D2 A8 VDDIN D3 A9 VDDOUT D4 A10 XIN32 D5 B1 ...
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Power Considerations 5.1 Power Supplies The SAM3U product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals ...
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Figure 5-1. Note: SAM3U Series 16 Single Supply Main Supply (1.62V-3.6V) Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ ...
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Figure 5-2. Note: 6430ES–ATARM–22-Aug-11 Core Externally Supplied Main Supply (1.62V-3.6V) VDDCORE Supply (1.62V-1.95V) Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main ...
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Figure 5-3. Note: SAM3U Series 18 Backup Batteries Used Backup Batteries VDDBU Main Supply (1.62V-3.6V) Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. ...
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Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to ...
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Entering Wait Mode: • Select the 4/8/12 MHz Fast RC Oscillator as Main Clock • Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR) • Execute the Wait-For-Event (WFE) instruction of the processor Note: 5.5.3 Sleep Mode ...
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Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set off sep- arately and wake up sources can be individually configured. of the configurations of the ...
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Wake-up Sources The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. Figure 5-4. Wake-up Source SMEN sm_int RTCEN rtc_alarm ...
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Fast Start-Up The SAM3U allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs. ...
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Input/Output Lines The SAM3U has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same GPIO line can be ...
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The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left uncon- nected for normal operations. ...
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Even in all low power modes, asserting the pin will automatically start-up the chip and erase the Flash. 7. Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit ...
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Matrix Slaves The Bus Matrix of the SAM3U manages 10 slaves. Each slave has its own arbiter, allowing a dif- ferent arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 Slave ...
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DMA Controller • Acting as one Matrix Master • Embeds 4 channels: – 3 channels with 8 bytes/FIFO for Channel Buffering – 1 channel with 32 bytes/FIFO for Channel Buffering • Linked List support with Status Write Back operation ...
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The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (Low to High priorities): Table 7-5. Instance name UART USART3 USART2 USART1 USART0 UART USART3 USART2 USART1 USART0 ADC12B 7.8 Debug and Test Features ...
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Product Mapping Figure 8-1. SAM3U Memory Mapping Code 0x00000000 Boot Memory 0x00080000 Internal Flash 0 0x00100000 Internal Flash 1 0x00180000 Internal ROM 0x00200000 Reserved 0x1FFFFFFF Internal SRAM 0x20000000 SRAM0 1 MByte 0x20080000 bit band region SRAM1 0x20100000 NFC (SRAM) ...
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Memories The embedded and external memories are described below. 9.1 Embedded Memories 9.1.1 Internal SRAM The SAM3U4 (256 KBytes internal Flash version) embeds a total of 48 Kbytes high-speed SRAM (32 Kbytes SRAM0 and 16 Kbytes SRAM1). The SAM3U2 ...
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The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32- bit internal bus. Its 128-bit wide memory interface increases performance. The user can choose between high performance or lower current consumption by selecting either 128-bit ...
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However safer to connect it directly to GND for the final application. 9.1.3.6 Calibration Bits NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed ...
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Boot Strategies The system always boots at address 0x0. To ensure a maximum boot possibilities the memory layout can be changed via GPNVM. A general purpose NVM (GPNVM1) bit is used to boot either on the ROM (default) or ...
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Error Report, including error flag, correctable error flag and word address being – Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte 10. System Controller The System Controller is a set of peripherals, which allow ...
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Figure 10-1. System Controller Block Diagram VDDBU FWUP SHDN NRSTB Zero-Power Power-on Reset General Purpose Backup Registers SLCK RTC SLCK RTT osc32k_xtal_en XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC osc32k_rc_en Oscillator Backup Power Supply vddcore_nreset NRST FSTT0 ...
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System Controller and Peripheral Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3U embeds three features to monitor, ...
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The Slow Clock generator is based kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the ...
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Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock HCLK • the Free running processor clock FCLK • the Cortex SysTick external clock • the Master Clock ...
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Watchdog Timer • 16-bit key-protected once-only Programmable Counter • Windowed, prevents the processor dead-lock on the watchdog access 10.8 SysTick Timer • 24-bit down counter • Self-reload capability • Flexible system timer 10.9 Real-time Timer ...
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... Table 10-1. • JTAG ID: 0x0582A03F Table 10-2. SAM3U4C (Rev A) SAM3U2C (Rev A) SAM3U1C (Rev A) SAM3U4E (Rev A) SAM3U2E (Rev A) SAM3U1E (Rev A) • JTAG ID: 0x0582A03F 10.14 PIO Controllers • 3 PIO Controllers, PIOA, PIOB, and PIOC, controlling a maximum of 96 I/O Lines • Each PIO Controller controls programmable I/O Lines – ...
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Peripherals 11.1 Peripheral Identifiers Table 11-1 the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some Peripherals are always clocked. Please ...
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Peripheral Signal Multiplexing on I/O Lines The SAM3U features 3 PIO controllers, PIOA, PIOB and PIOC that multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to ...
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PIO Controller A Multiplexing Table 11-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A PA0 TIOB0 PA1 TIOA0 PA2 TCLK0 PA3 MCCK PA4 MCCDA PA5 MCDA0 PA6 MCDA1 PA7 MCDA2 PA8 MCDA3 PA9 TWD0 PA10 TWCK0 PA11 ...
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PIO Controller B Multiplexing Table 11-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A PB0 PWMH0 PB1 PWMH1 PB2 PWMH2 PWMH3 PB3 TCLK1 PB4 PB5 TIOA1 TIOB1 PB6 RTS0 PB7 PB8 CTS0 PB9 D0 D1 PB10 PB11 ...
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PIO Controller C Multiplexing Table 11-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 A2 PC1 A3 PC2 A4 A5 PC3 A6 PC4 PC5 A7 A8 PC6 A9 PC7 PC8 A10 PC9 A11 A12 PC10 PC11 ...
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Embedded Peripherals Overview 12.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – ...
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Universal Synchronous Asynchronous Receiver Transmitter (USART) • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode stop bits in Synchronous ...
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Pulse Generation – Delay Timing – Pulse Width Modulation – Up/Down Capabilities – Quadrature Decoder Logic • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • ...
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High Speed Multimedia Card Interface (HSMCI) • Compatibility with MultiMedia Card Specification Version 4.3 • Compatibility with SD Memory Card Specification Version 2.0 • Compatibility with SDIO Specification Version V2.0. • Compatibility with CE-ATA Specification 1.1 • Cards clock ...
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Analog-to-Digital Converter (ADC) Two ADCs are embedded in the product. 12.10.1 12-bit High Speed ADC • 8-channel ADC • 12-bit 1 Msamples/sec. Cyclic Pipeline ADC • Integrated 8-to-1 multiplexer • 12-bit resolution • Selectable single ended or differential input ...
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Package Drawings Figure 13-1. 100-ball LQFP Package Drawing SAM3U Series 52 6430ES–ATARM–22-Aug-11 ...
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Figure 13-2. 100-ball LFBGA Package Drawing 6430ES–ATARM–22-Aug-11 SAM3U Series 53 ...
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Figure 13-3. 144-lead LQFP Package Drawing Notes: 1. This drawing is for general information only; refer to JEDEe Drawing MS-026 for additional information. 2. The top package body size may be smaller than the bottom package size by as much ...
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Figure 13-4. 144-ball LFBGA Package Drawing All dimensions are in mm. 6430ES–ATARM–22-Aug-11 SAM3U Series 55 ...
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... Ordering Information Table 14-1. ATSAM3U4/2/1 Ordering Information Ordering Code MRL ATSAM3U4EA-AU A ATSAM3U4EA-CU A ATSAM3U4CA-AU A ATSAM3U4CA-CU A ATSAM3U2EA-AU A ATSAM3U2EA-CU A ATSAM3U2CA-AU A ATSAM3U2CA-CU A ATSAM3U1EA-AU A ATSAM3U1EA-CU A ATSAM3U1CA-AU A ATSAM3U1CA-CU A SAM3U Series 56 Flash (Kbytes) Package 256 LQFP144 256 LFBGA 144 256 LQFP 100 256 TFBGA100 128 LQFP144 128 LFBGA144 128 ...
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Revision History In the tables that follow, the most recent version of the document appears first. “rfo” indicates changes requested during the review and approval loop. Doc. Rev 6430ES Comments Comment in front of rows PA24 and PA25 removed, and ...
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Doc Rev 6430BS Comments Introduction: Section 1. ”SAM3U Description”, Updated: 52 Kbytes of SRAM. 4x USARTs (SAM3U1C/2C/4C have 3 TWIs (SAM3U1C/2C/4C have 1 SPIs SAM3U1C/2C/4C have 4), Table 1-1, “Configuration SAM3U4/3/2C rows FWUP replaces ...
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