SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 109
SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
When
Condition Flags
If
Examples
Multiword arithmetic examples
The example below shows two instructions that add a 64-bit integer contained in
another 64-bit integer contained in
64-bit addition example:
Multiword values do not have to use consecutive registers. The example below shows instruc-
tions that subtract a 96-bit integer contained in R9, R1, and R11 from another contained in R6,
R2, and R8. The example stores the result in R6, R9, and R2.
96-bit subtraction example:
• with the exception of the
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
S
ADD
SUBS
RSB
ADCHI R11, R0, R3
ADDS
ADC
SUBS
SBCS
SBC
only with the additional restrictions:
is specified, these instructions update the N, Z, C and V flags according to the result.
– if the instruction is conditional, it must be the last instruction in the IT block
– the user must not specify the S suffix
– the second operand must be a constant in the range 0 to 4095.
– Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are
– Note: To generate the address of an instruction, the constant based on the value of
Rd
rounded to
calculation word-aligned.
the PC must be adjusted. ARM recommends to use the
ADD
the correct constant for the
is PC in the
R4, R4, #1280
R2, R8, R11
R2, R1, R3
R5, R1, R3
R8, R6, #240
R6, R6, R9
R9, R2, R1
R4, R0, R2
or
SUB
with
0b00
; flag clear.
ADD{cond} PC, PC, Rm
Rn
before performing the calculation, making the base address for the
; add the most significant words with carry
; add the least significant words
; subtract the most significant words with carry
; subtract the least significant words
; subtract the middle words with carry
equal to the PC, because the assembler automatically calculates
ADD{cond} PC, PC, Rm
; Subtracts contents of R4 from 1280
; Sets the flags on the result
; Only executed if C flag set and Z
R0
ADR
and
instruction.
instruction:
R1
, and place the result in
instruction,
Rn
can be PC only in
ADR
instruction instead of
R4
and
R5
.
ADD
SAM4S
SAM4S
and
R2
and
SUB
, and
R3
109
109
to
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