SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 485

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.2.5
26.2.6
26.2.7
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Processor Clock Controller
SysTick Clock
USB Clock Controller
Figure 26-6. Master Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep
Mode. The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the
WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup
Mode Register (PMC_FSMR).
The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Sleep Mode is achieved by disabling the Processor Clock,
which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the
product.
When Processor Sleep Mode is entered, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The SysTick calibration value is fixed to 12500 which allows the generation of a time base of 1
ms with SysTick clock to the maximum frequency on MCK divided by 8.
The user can select the PLLA or the PLLB output as the USB Source Clock by writing the USBS
bit in PMC_USB. If using the USB, the user must program the PLL to generate an appropriate
frequency depending on the USBDIV bit in PMC_USB.
When the PLL output is stable, i.e., the LOCK bit is set:
• The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP
bit in PMC_SCSR gives the activity of this clock. The USB device port requires both the 48
MHz signal and the Master Clock. The Master Clock may be controlled by means of the
Master Clock Controller.
MAINCK
PLLACK
PLLBCK
SLCK
PMC_MCKR
CSS
PMC_MCKR
Master Clock
Prescaler
PRES
MCK
To the Processor
Clock Controller (PCK)
SAM4S
SAM4S
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