SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 542

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
28.5.7
Figure 28-4. Output Line Timings
28.5.8
28.5.9
542
542
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Write PIO_CODR
Write PIO_SODR
SAM4S
SAM4S
Output Line Timings
Inputs
Input Glitch and Debouncing Filters
PIO_ODSR
PIO_PDSR
MCK
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
Figure 28-4
directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is
set.
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the
debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow
Clock.
The selection between glitch filtering or debounce filtering is done by writing in the registers
PIO_IFSCDR (PIO Input Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter
Slow Clock Enable Register). Writing PIO_IFSCDR and PIO_IFSCER respectively, sets and
clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter
Slow Clock Status Register).
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV
field of the PIO_SCDR (Slow Clock Divider Register)
• If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period
• If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2
of Master Clock.
Period of the Programmable Divided Slow Clock.
Figure 28-4
APB Access
shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by
also shows when the feedback in PIO_PDSR is available.
2 cycles
APB Access
2 cycles
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11

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