SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 62

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.4.2.6
11.4.2.7
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62
Directly Accessing a Bit-band Region
Little-endian Format
SAM4S
SAM4S
Memory Endianness
Synchronization Primitives
“Behavior of Memory Accesses”
accesses to the bit-band regions.
The processor views memory as a linear collection of bytes numbered in ascending order from
zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored
word.
In little-endian format, the processor stores the least significant byte of a word at the lowest-
numbered byte, and the most significant byte at the highest-numbered byte. For example:
The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-
blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. The software can use them to perform a guaranteed read-modify-write memory update
sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-exclusive Instruction, used to read the value of a memory location, requesting exclu-
sive access to that location.
A Store-Exclusive instruction, used to attempt to write to the same memory location, returning
a status bit to a register. If this bit is:
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The software must use a Load-Exclusive instruction with the corresponding Store-Exclusive
instruction.
Address A
• 0: it indicates that the thread or process gained exclusive access to the memory, and the
• 1: it indicates that the thread or process did not gain exclusive access to the memory, and no
• the word instructions LDREX and STREX
• the halfword instructions LDREXH and STREXH
• the byte instructions LDREXB and STREXB.
write succeeds,
write is performed.
A+3
A+2
A+1
“Little-endian Format”
7
Memory
B0
B1
B2
B3
0
lsbyte
msbyte
31
describes how words of data are stored in memory.
B3
24 23
describes the behavior of direct byte, halfword, or word
B2
Register
16 15
B1
8 7
B0
0
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11