SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 73

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Table 11-11. Faults (Continued)
Notes:
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
Fault
MPU or default memory map mismatch:
Bus error:
Precise data bus error
Imprecise data bus error
Attempt to access a coprocessor
Undefined instruction
Attempt to enter an invalid instruction set state
Invalid EXC_RETURN value
Illegal unaligned load or store
Divide By 0
Fault Escalation and Hard Faults
on instruction access
on data access
during exception stacking
during exception unstacking
during lazy floating-point state preservation
during exception stacking
during exception unstacking
during instruction prefetch
during lazy floating-point state preservation
1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction with
ICI continuation.
All faults exceptions except for hard fault have configurable exception priority, see
dler Priority Registers”
see
Usually, the exception priority, together with the values of the exception mask registers, deter-
mines whether the processor enters the fault handler, and whether a fault handler can preempt
another fault handler, as described in
In some situations, a fault with configurable priority is treated as a hard fault. This is called prior-
ity escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
• A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
• A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is
• An exception handler causes a fault for which the priority is the same as or lower than the
fault occurs because a fault handler cannot preempt itself; it must have the same priority as
the current priority level.
because the handler for the new fault cannot preempt the currently executing fault handler.
currently executing exception.
“System Handler Control and State Register”
(1)
Handler
Memory
management
fault
Bus fault
Usage fault
. The software can disable the execution of the handlers for these faults,
Bit Name
-
IACCVIOL
DACCVIOL
MSTKERR
MUNSKERR
MLSPERR
-
STKERR
UNSTKERR
IBUSERR
LSPERR
PRECISERR
IMPRECISERR
NOCP
UNDEFINSTR
INVSTATE
INVPC
UNALIGNED
DIVBYZERO
“Exception Model”
(2)
.
Fault Status Register
-
“MMFSR: Memory Management Fault
Status Subregister”
-
“BFSR: Bus Fault Status Subregister”
“UFSR: Usage Fault Status Subregister”
.
SAM4S
SAM4S
“System Han-
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