SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 27

• Manufacturer Part Number: SAM4S16C
• Manufacturer: Atmel Corporation

Specifications of SAM4S16C

• Flash (kbytes): 1024 Kbytes
• Pin Count: 100
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7. Processor and Architecture
7.1
7.2
7.3
7.4
11100AS–ATARM–27-Oct-11
ARM Cortex-M4 Processor
APB/AHB bridge
Matrix Masters
Matrix Slaves
The SAM4S embeds One Peripheral bridge.
The peripherals of the bridge are clocked by MCK.
The Bus Matrix of the SAM4S manages 4 masters, which means that each master can perform
an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
Table 7-1.
The Bus Matrix of the SAM4S manages 5 slaves. Each slave has its own arbiter, allowing a dif-
ferent arbitration per slave.
Table 7-2.
Master 0
Master 1
Master 2
Master 3
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store
• Three-stage pipeline
• Saturating arithmetic for signal processing
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Thumb and Debug states
• Handler and Thread modes
• Low latency ISR entry and exit
List of Bus Matrix Masters
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
Internal Flash
External Bus Interface
Peripheral Bridge
Cortex-M4 Instruction/Data
Cortex-M4 System
Peripheral DMA Controller (PDC)
CRC Calculation Unit
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