SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 42

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SAM4S16C

Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM4S16C

Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.10 Real Time Clock
10.11 General-Purpose Backup Registers
10.12 Nested Vectored Interrupt Controller
10.13 Chip Identification
Table 10-1.
42
• JTAG ID: 05B3_203F
Chip Name
SAM4S16A
SAM4S16B
SAM4S16C
SAM4S8B
SAM4S8C
SAM4S8A
SAM4S Chip IDs Register
• Low power consumption
• Full asynchronous design
• Two hundred year Gregorian and Persian calendar
• Programmable Periodic Interrupt
• Trimmable 32.7682 kHz crystal oscillator clock source
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
• Waveform output capability on GPIO pins in low power modes
• Eight 32-bit backup general-purpose registers
• Thirty maskable external interrupts
• Sixteen priority levels
• Processor state automatically saved on interrupt entry, and restored on
• Dynamic reprioritizing of interrupts
• Priority grouping.
• Support for tail-chaining and late arrival of interrupts.
• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no
• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.
instruction overhead.
– Alarm Register capable to generate a wake-up of the system through the Shut Down
– selection of pre-empting interrupt levels and non pre-empting interrupt levels.
– back-to-back interrupt processing without the overhead of state saving and
Controller
restoration between interrupts.
Flash Size
(KBytes)
1024
1024
1024
512
512
512
RAM Size
(KBytes)
128
128
128
128
128
128
Pin Count
100
100
48
64
48
64
0x28AC_0CE0
0x288C_0CE0
0x289C_0CE0
0x288C_0AE0
0x289C_0AE0
0x28AC_0AE0
CHIPID_CIDR
11100AS–ATARM–27-Oct-11
CHIPID_EXID
0x0
0x0
0x0
0x0
0x0
0x0

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