SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet

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SAM9RL64

Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9RL64

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
ARM7TDMI
(Rev 3)
Technical Reference Manual
Copyright © 1994-2001. All rights reserved.
ARM DDI 0029G

Related parts for SAM9RL64

SAM9RL64 Summary of contents

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Technical Reference Manual Copyright © 1994-2001. All rights reserved. ARM DDI 0029G ARM7TDMI (Rev 3) ...

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ARM7TDMI Technical Reference Manual Copyright © 1994-2001. All rights reserved. Release Information Date October 1994 December 1994 December 1994 March 1995 August 1995 November 2000 April 2001 Proprietary Notice Words and logos marked with brands and names mentioned herein may ...

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Confidentiality Status This document is Open Access. This document has no restriction on distribution. Product Status The information in this document is final (information on a developed product). Web Address ARM DDI 0029G Copyright © 1994-2001. All rights reserved. iii ...

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Copyright © 1994-2001. All rights reserved. ARM DDI 0029G ...

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Contents ARM7TDMI Technical Reference Manual Preface Chapter 1 Introduction 1.1 1.2 1.3 1.4 Chapter 2 Programmer’s Model 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 ARM DDI 0029G About this document .................................................................................. xviii Further reading ............................................................................................ xxi Feedback ...

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Contents Chapter 3 Memory Interface 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 Chapter 4 Coprocessor Interface 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Chapter 5 Debug Interface 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Chapter ...

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Chapter 7 AC and DC Parameters 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 Appendix A ...

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Contents B.8 B.9 B.10 B.11 B.12 B.13 B.14 B.15 B.16 B.17 B.18 B.19 Glossary viii Determining the core and system state .................................................... B-24 Behavior of the program counter during debug ........................................ B-29 Priorities and exceptions .......................................................................... B-32 Scan chain cell ...

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List of Tables ARM7TDMI Technical Reference Manual Change history .............................................................................................................. ii Table 1-1 Key to tables ........................................................................................................... 1-10 Table 1-2 ARM instruction summary ....................................................................................... 1-12 Table 1-3 Addressing modes .................................................................................................. 1-15 Table 1-4 Operand 2 ............................................................................................................... 1-18 Table 1-5 Fields ...

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List of Tables Table 4-3 Summary of coprocessor signaling ........................................................................... 4-7 Table 4-4 Mode identifier signal meanings (nTRANS) ............................................................ 4-17 Table 5-1 DCC register access instructions ............................................................................ 5-17 Table 6-1 Branch instruction cycle operations .......................................................................... 6-4 Table 6-2 Thumb long ...

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Table 7-22 APE control timing parameters ............................................................................... 7-27 Table 7-23 AC timing parameters used in this chapter ............................................................. 7-28 Table A-1 Transistor sizes ......................................................................................................... A-2 Table A-2 Signal types ............................................................................................................... A-2 Table A-3 Signal Descriptions ................................................................................................... A-3 Table B-1 Public ...

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List of Tables xii Copyright © 1994-2001. All rights reserved. ARM DDI 0029G ...

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List of Figures ARM7TDMI Technical Reference Manual Figure P-1 Key to timing diagram conventions ............................................................................. xx Figure 1-1 Instruction pipeline .................................................................................................... 1-3 Figure 1-2 ARM7TDMI processor block diagram ....................................................................... 1-7 Figure 1-3 Main processor .......................................................................................................... 1-8 Figure 1-4 ARM7TDMI processor ...

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List of Figures Figure 3-11 External bus arrangement ...................................................................................... 3-17 Figure 3-12 Bidirectional bus timing ........................................................................................... 3-18 Figure 3-13 Unidirectional bus timing ......................................................................................... 3-18 Figure 3-14 External connection of unidirectional buses ........................................................... 3-19 Figure 3-15 Data write bus cycle ................................................................................................ ...

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Figure 7-23 APE control timing ................................................................................................... 7-27 Figure B-1 ARM7TDMI core scan chain arrangements .............................................................. B-4 Figure B-2 Test access port controller state transitions .............................................................. B-5 Figure B-3 ID code register format ............................................................................................ B-14 Figure B-4 Input scan cell ......................................................................................................... ...

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List of Figures xvi Copyright © 1994-2001. All rights reserved. ARM DDI 0029G ...

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Preface This preface introduces the ARM7TDMI core and its reference documentation. It contains the following sections: • About this document on page xviii • Further reading on page xxi • Feedback on page xxii. ARM DDI 0029G Copyright © 1994-2001. ...

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Preface About this document This document is a reference manual for the ARM7TDMI core. Intended audience This document has been written for experienced hardware and software engineers who are working with the ARM7TDMI processor. Using this manual This document is ...

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Typographical conventions The following typographical conventions are used in this book: italic bold typewriter italic typewriter bold ARM DDI 0029G Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. Highlights interface elements, such as menu names and buttons. ...

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Preface Timing diagram conventions The key provided in Figure P-1 explains the components used in timing diagrams. Any variations are labeled when they occur. Therefore, no additional meaning must be attached unless specifically stated. Shaded bus and signal areas are ...

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Further reading This section lists publications by ARM Limited and third parties. ARM periodically provides updates and corrections to its documentation. For current errata sheets, addenda, and list of Frequently Asked Questions go to the ARM website: ARM publications This ...

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Preface Feedback ARM Limited welcomes feedback both on the ARM7TDMI core, and on the documentation. Feedback on the ARM7TDMI core If you have any comments or suggestions about this product, please contact your supplier giving: • the product name • ...

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Chapter 1 Introduction This chapter introduces the ARM7TDMI core. It contains the following sections: • About the ARM7TDMI core on page 1-2 • Architecture on page 1-5 • Block, core, and functional diagrams on page 1-7 • Instruction set summary ...

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Introduction 1.1 About the ARM7TDMI core The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit microprocessors. The ARM family offers high performance for very low power consumption, and small size. The ARM architecture is based on ...

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During normal operation, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The program counter points to the instruction being fetched rather than to the instruction being executed. This ...

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Introduction 1.1.3 Memory interface The ARM7TDMI processor memory interface has been designed to allow performance potential to be realized, while minimizing the use of memory. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard ...

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Architecture The ARM7TDMI processor has two instruction sets: • the 32-bit ARM instruction set • the 16-bit Thumb instruction set. The ARM7TDMI processor is an implementation of the ARMv4T architecture. For full details of both the ARM and Thumb ...

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Introduction Thumb therefore offers a long branch range, powerful arithmetic operations, and a large address space. Thumb code is typically 65% of the size of ARM code, and provides 160% of the performance of ARM code when running from a ...

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Block, core, and functional diagrams The ARM7TDMI processor architecture, core, and functional diagrams are illustrated in the following figures: • Figure 1-2 shows a block diagram of the ARM7TDMI processor components and major signal paths • Figure 1-3 on ...

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Introduction nENOUT 1-8 A[31:0] ALE ABE Address register Address incrementer Register bank (31 x 32-bit registers) (6 status registers Multiplier Barrel shifter 32-bit ALU Write data register Thumb instruction controller DBE nENIN Copyright © 1994-2001. All rights ...

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Clocks and timing Interrupts Bus controls Power Debug ARM DDI 0029G MCLK nWAIT ECLK nIRQ nFIQ ISYNC nRESET BUSEN HIGHZ nHIGHZ BIGEND nENIN nENOUT nENOUTI ABE ALE APE DBE ARM7TDMI TBE BUSDIS ECAPCLK DBGRQ BREAKPT DBGACK ...

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Introduction 1.4 Instruction set summary This section provides a description of the instruction sets used on the ARM7TDMI processor. This section describes: • Format summary on page 1-10 • ARM instruction summary on page 1-12 • Thumb instruction summary on ...

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Refer to the ARM Architectural Reference Manual for more information about the ARM instruction set formats ...

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Introduction Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a multiply instruction with bit 6 changed These instructions must not be used because their action might ...

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Operation Multiply unsigned accumulate long Multiply signed long Multiply signed accumulate long Compare Compare negative Logical Test Test equivalence AND EOR ORR Bit clear Branch Branch Branch with link Branch and exchange instruction set Load Word Word with user-mode privilege ...

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Introduction Operation • Decrement after • Stack operation • Stack operation, and restore CPSR • Stack operation with user registers Store Word Word with user-mode privilege Byte Byte with user-mode privilege Halfword Multiple block data operations • Increment before • ...

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Addressing modes The addressing modes are procedures shared by different instructions for generating values used by the instructions. The five addressing modes used by the ARM7TDMI processor are: Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 The addressing ...

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Introduction Addressing mode Mode 2, privileged <a_mode2P> 1-16 Table 1-3 Addressing modes (continued) Type or addressing mode Immediate Register Scaled register Immediate offset Register offset Scaled register offset Post-indexed offset Immediate Register Scaled register Copyright © 1994-2001. All rights reserved. ...

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Addressing mode Mode 3, <a_mode3> Mode 4, load <a_mode4L> Mode 4, store <a_mode4S> Mode 5, coprocessor data transfer <a_mode5> ARM DDI 0029G Table 1-3 Addressing modes (continued) Type or addressing mode Immediate offset Pre-indexed Post-indexed Register Pre-indexed Post-indexed IA, increment ...

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Introduction Operand 2 An operand is the part of the instruction that references data or a peripheral device. Operand 2 is listed in Table 1-4. Fields Fields are listed in Table 1-5. 1-18 Operand Operand 2 <Oprnd2> Type Field {field} ...

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Condition fields Condition fields are listed in Table 1-6. Field type Suffix Condition {cond 1.4.3 Thumb instruction summary The Thumb instruction set formats are shown ...

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Introduction Move, compare, add, and subtract High register operations and branch Load and store with relative offset Load and store sign-extended byte and Load and store with immediate offset Load and store halfword SP-relative load and store Add offset to ...

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The Thumb instruction set summary is listed in Table 1-7. Operation Move Immediate High to Low Low to High High to High Arithmetic Add Add Low, and Low Add High to Low Add Low to High Add High to High ...

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Introduction Operation EOR OR Bit clear Move NOT Test bits Shift/Rotate Logical shift left Logical shift right Arithmetic shift right Rotate right Branch Conditional • set • clear • set • clear ...

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Operation Unconditional Long branch with link Optional state change • to address held in Lo reg • to address held in Hi reg Load With immediate offset • word • halfword • byte With register offset • word • halfword ...

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Introduction Operation With register offset • word • halfword • byte SP-relative Multiple Push/Pop Push registers onto stack Push LR, and registers onto stack Pop registers from stack Pop registers, and PC from stack Software Interrupt - 1-24 Table 1-7 ...

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Chapter 2 Programmer’s Model This chapter describes the ARM7TDMI core programmer’s model. It contains the following sections: • About the programmer’s model on page 2-2 • Processor operating states on page 2-3 • Memory formats on page 2-4 • Data ...

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Programmer’s Model 2.1 About the programmer’s model The ARM7TDMI processor core implements ARM architecture v4T, which includes the 32-bit ARM instruction set, and the 16-bit Thumb instruction set. The programmer’s model is described in the ARM Architecture Reference Manual. 2-2 ...

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Processor operating states The ARM7TDMI processor has two operating states: ARM Thumb In Thumb state, the Program Counter (PC) uses bit 1 to select between alternate halfwords. Transition between ARM and Thumb states does not affect the processor mode ...

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Programmer’s Model 2.3 Memory formats The ARM7TDMI processor views memory as a linear collection of bytes numbered in ascending order from zero. For example: • bytes zero to three hold the first stored word • bytes four to seven hold ...

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Big-Endian In big-endian format, the ARM7TDMI processor stores the most significant byte of a word at the lowest-numbered byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory system connects ...

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Programmer’s Model 2.4 Data types The ARM7TDMI processor supports the following data types: • words, 32-bit • halfwords, 16-bit • bytes, 8-bit. You must align these as follows: • word quantities must be aligned to four-byte boundaries • halfword quantities ...

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Operating modes The ARM7TDMI processor has seven modes of operation: • User mode is the usual ARM program execution state, and is used for executing most application programs. • Fast Interrupt (FIQ) mode supports a data transfer or channel ...

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Programmer’s Model 2.6 Registers The ARM7TDMI processor has a total of 37 registers: • 31 general-purpose 32-bit registers • 6 status registers. These registers are not all accessible at the same time. The processor state and operating mode determine which ...

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FIQ mode has seven banked registers mapped to r8–r14 (r8_fiq–r14_fiq). In ARM state, many FIQ handlers do not have to save any registers. The User, IRQ, Supervisor, Abort, and undefined modes each have two banked registers mapped to r13 and ...

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Programmer’s Model 2.6.2 The Thumb-state register set The Thumb-state register set is a subset of the ARM-state set. The programmer has access to: • 8 general registers, r0–r7 • the PC • the SP • the LR • the CPSR. ...

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The relationship between ARM-state and Thumb-state registers The Thumb-state registers relate to the ARM-state registers in the following way: • Thumb-state r0–r7 and ARM-state r0–r7 are identical • Thumb-state CPSR and SPSRs and ARM-state CPSR and SPSRs are identical ...

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Programmer’s Model Registers r0–r7 are known as the low registers. Registers r8–r15 are known as the high registers. 2.6.4 Accessing high registers in Thumb state In Thumb state, the high registers, r8–r15, are not part of the standard register set. ...

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The program status registers The ARM7TDMI processor contains a CPSR and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of ...

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Programmer’s Model All instructions can execute conditionally in ARM state. In Thumb state, only the Branch instruction can be executed conditionally. For more information about conditional execution, refer to the ARM Architecture Reference Manual. 2.7.2 Control bits The bottom eight ...

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Mode bits Bits M[4:0] determine the processor operating mode as shown in Table 2-2. Not all combinations of the mode bits define a valid processor mode, so take care to use only the bit combinations shown. M[4:0] Mode Visible Thumb-state ...

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Programmer’s Model 2.8 Exceptions Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example, to service an interrupt from a peripheral. Before attempting to handle an exception, the ARM7TDMI processor preserves the current processor ...

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Exception Return instruction or entry FIQ IRQ DABT RESET Not applicable 2.8.2 Entering an exception The ARM7TDMI processor handles an exception as follows: 1. Preserves the address of the next instruction in the appropriate LR. When the exception entry is ...

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Programmer’s Model Exceptions are always entered in ARM state. When the processor is in Thumb state and an exception occurs, the switch to ARM state takes place automatically when the exception vector address is loaded into the PC. An exception ...

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Interrupt request The Interrupt Request (IRQ) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ, and is masked on entry to an FIQ sequence. As with the ...

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Programmer’s Model Prefetch Abort When a Prefetch Abort occurs, the ARM7TDMI processor marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, ...

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Software interrupt instruction The Software Interrupt instruction (SWI) is used to enter Supervisor mode, usually to request a particular supervisor function. The SWI handler reads the opcode to extract the SWI function number. A SWI handler returns by executing ...

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Programmer’s Model Address 2.8.10 Exception priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled. The priority order is listed in Table 2-5. Some exceptions cannot occur together: • ...

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Interrupt latencies The calculations for maximum and minimum latency are described in: • Maximum interrupt latencies on page 2-23 • Minimum interrupt latencies on page 2-23. 2.9.1 Maximum interrupt latencies When FIQs are enabled, the worst-case latency for FIQ ...

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Programmer’s Model 2.10 Reset When the nRESET signal goes LOW a reset occurs, and the ARM7TDMI core abandons the executing instruction and continues to increment the address bus as if still fetching word or halfword instructions. nMREQ and SEQ indicates ...

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Chapter 3 Memory Interface This chapter describes the ARM7TDMI processor memory interface. It contains the following sections: • About the memory interface on page 3-2 • Bus interface signals on page 3-3 • Bus cycle types on page 3-4 • ...

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Memory Interface 3.1 About the memory interface The ARM7TDMI processor has a Von Neumann architecture, with a single 32-bit data bus carrying both instructions and data. Only load, store, and swap instructions can access data from memory. 3-2 Copyright © ...

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Bus interface signals The signals in the ARM7TDMI processor bus interface can be grouped into four categories: • clocking and clock control • address class signals • memory request signals • data timed signals. The clocking and clock control ...

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Memory Interface 3.3 Bus cycle types The ARM7TDMI processor bus interface is pipelined. This gives the maximum time for a memory cycle to decode the address and respond to the access request: • memory request signals are broadcast in the ...

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Bus cycle types are encoded on the nMREQ and SEQ signals as listed in Table 3-1. A memory controller for the ARM7TDMI processor must commit to a memory access only on an N-cycle or an S-cycle. 3.3.1 Nonsequential cycles A ...

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Memory Interface The ARM7TDMI processor can perform back-to-back, nonsequential memory cycles. This happens, for example, when an memory controller for the ARM7TDMI core, and your memory system is unable to cope with this case, use the nWAIT signal to extend ...

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The possible burst types are listed in Table 3-2. Burst type Word read Word write Halfword read All accesses in a burst are of the same data width, direction, and protection type. For more details, see Addressing signals on page ...

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Memory Interface Where possible the ARM7TDMI processor broadcasts the address for the next access, so that decode can start, but the memory controller must not commit to a memory access. This is shown in Figure 3-4 and, is further described ...

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When designing a memory controller, ensure that the design also works when an I-cycle is followed by an N-cycle to a different address. This sequence can occur during exceptions, or during writes to the PC essential that the ...

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Memory Interface 3.3.6 Summary of ARM memory cycle timing A summary of ARM7TDMI processor memory cycle timing is shown in Figure 3-7. MCLK A[31:0] nMREQ nRAS nCAS D[31:0] 3-10 Figure 3-6 Coprocessor register transfer cycles N-cycle a SEQ Copyright © ...

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Addressing signals The address class signals are: • A[31:0] on page 3-11 • nRW on page 3-11 • MAS[1:0] on page 3-11 • nOPC on page 3-12 • nTRANS on page 3-13 • LOCK on page 3-13 • TBIT ...

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Memory Interface The address produced by the processor is always a byte address. However, the memory system must ignore the bottom redundant bits of the address. The significant address bits are listed in Table 3-3. The size of transfer does ...

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The nTRANS output conveys information about the transfer. A MMU can use this signal to determine whether an access is from a privileged mode or User mode. This signal can be used with nOPC to implement an access ...

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Memory Interface 3.5 Address timing The ARM7TDMI processor address bus can operate in one of two configurations: • pipelined • depipelined. ARM Limited strongly recommends that pipelined address timing is used in new design to obtain optimum system performance. ARM ...

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The AMBA specification for Advanced High-performance Bus (AHB) and Advanced System Bus (ASB) requires a pipelined address bus. This means that APE must be configured HIGH. Many systems contain a mixture of DRAM, SRAM and ROM. To cater for the ...

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Memory Interface If ALE used to change address timing, then you must tie APE HIGH. Similarly, if APE used, ALE must be tied HIGH. You can obtain better system performance when the address pipeline ...

Page 87

Data timed signals This section describes: • D[31:0], DOUT[31:0], and DIN[31:0] on page 3-17 • ABORT on page 3-24 • Byte latch enables on page 3-24 • Byte and halfword accesses on page 3-26. 3.6.1 D[31:0], DOUT[31:0], and DIN[31:0] ...

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Memory Interface Unidirectional data bus When BUSEN is HIGH, all instructions and input data are presented on the input data bus, DIN[31:0]. The timing of this data is similar to that of the bidirectional bus when in input mode. Data ...

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Bidirectional data bus When BUSEN is LOW, the buffer between DIN[31:0] and D[31:0] is disabled. Any data presented on DIN[31:0] is ignored. Also, when BUSEN is LOW, the value on DOUT[31:0] is forced to When the ARM7TDMI processor is reading ...

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Memory Interface 3-20 MCLK A[31:0] nRW nENOUT D[31:0] ARM7TDMI data direction control from core write data from core read data to core Copyright © 1994-2001. All rights reserved. memory cycle Figure 3-15 Data write bus cycle scan DBE cell scan ...

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The macrocell has an additional bus control signal, nENIN that allows the external system to manually tristate the bus. In the simplest systems, nENIN can be tied LOW and nENOUT can be ignored. In many applications, when the external data ...

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Memory Interface ARM7TDMI core test chip example system Connecting the ARM7TDMI processor data bus, D[31: external shared bus requires additional logic that varies between applications in the case of a test chip. In this application, care must be ...

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ARM7TDMI test chip or product ARM7TDMI core scan cell scan cell scan cell At the core level, TBE and DBE are inactive, tied HIGH, because in a packaged part you do not have to manually force the internal buses into ...

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Memory Interface 3.6.2 ABORT ABORT indicates that a memory transaction failed to complete successfully. ABORT is sampled at the end of the bus cycle during S-cycles and N-cycles. If ABORT is asserted on a data access, it causes the processor ...

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Because two memory cycles are required, nWAIT is used to stretch the internal processor clock. nWAIT does not affect the operation of the data latches. Using this method, data can be taken from memory as word, halfword, or byte at ...

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Memory Interface MCLK APE nMREQ SEQ A[31:0] nWAIT D[7:0] D[15:8] BL[3:0] 3.6.4 Byte and halfword accesses The processor indicates the size of a transfer by use of the MAS[1:0] signal as described in MAS[1:0] on page 3-11. Byte, halfword, and ...

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Access type Word Halfword Byte For subword reads the value is placed in the ARM register in the least significant bits regardless of the byte lane used to read the data. For example, a byte read on A[1: ...

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Memory Interface 3-28 16 Bits Byte write (register [7:0 D[31:24] D[23:16] Half word write (register [15:0]) CD D[31:16] Word write (register [31:0]) ABCD D[31:0] Copyright © 1994-2001. All rights reserved ...

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Stretching access times The ARM7TDMI processor does not contain any dynamic logic that relies on regular clocking to maintain the internal state. Therefore, there is no limit upon the maximum period for which MCLK can be stretched, or nWAIT ...

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Memory Interface MCLK nWAIT nMREQ SEQ A[31:0] nRW D[31:0] nRAS nCAS When designing a memory controller, you are strongly advised to sample the values of nMREQ, SEQ, and the address class signals only when nWAIT is HIGH. This ensures that ...

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Action of ARM7TDMI core in debug state When the ARM7TDMI core is in debug state, nMREQ and SEQ are forced to indicate internal cycles. This allows the rest of the memory system to ignore the processor and function as ...

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Memory Interface 3.9 Privileged mode access ARM Limited usually recommends that if only privileged mode access is required from a memory system then you are advised to use the nTRANS pin on the core. This signal distinguishes between User and ...

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Reset sequence after power good practice to reset a static device immediately on power-up, to remove any undefined conditions within the device that can otherwise combine to cause a DC path and consequently increase current consumption. ...

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Memory Interface 3-34 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G ...

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Chapter 4 Coprocessor Interface This chapter describes the ARM7TDMI core coprocessor interface. It contains the following sections: • About coprocessors on page 4-2 • Coprocessor interface signals on page 4-4 • Pipeline following signals on page 4-5 • Coprocessor interface ...

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Coprocessor Interface 4.1 About coprocessors The ARM7TDMI core instruction set enables you to implement specialized additional instructions using coprocessors to extend functionality. These are separate processing units that are tightly coupled to the ARM7TDMI processor. A typical coprocessor contains: • ...

Page 107

Coprocessor availability coprocessors can be referenced by a system, each with a unique coprocessor ID number to identify it. The ARM7TDMI core contains one internal coprocessor: • CP14, the debug communications channel coprocessor. Other coprocessor numbers ...

Page 108

Coprocessor Interface 4.2 Coprocessor interface signals The signals used to interface the ARM7TDMI core to a coprocessor are grouped into four categories. The clock and clock control signals are: • MCLK • nWAIT • nRESET. The pipeline following signals are: ...

Page 109

Pipeline following signals Every coprocessor in the system must contain a pipeline follower to track the instructions in the ARM7TDMI processor pipeline. The coprocessors connect to the configured ARM7TDMI core input data bus, D[31:0] or DIN[31:0], over which instructions ...

Page 110

Coprocessor Interface 4.4 Coprocessor interface handshaking Coprocessor interface handshaking is described as follows: • The coprocessor on page 4-6 • The ARM7TDMI processor on page 4-7 • Coprocessor signaling on page 4-7 • Consequences of busy-waiting on page 4-8 • ...

Page 111

The ARM7TDMI processor Coprocessor instructions progress down the ARM7TDMI core pipeline in step with the coprocessor pipeline. A coprocessor instruction is executed if the following are true: 1. The coprocessor instruction has reached the Execute stage of the pipeline. ...

Page 112

Coprocessor Interface MCLK Fetch stage ADD SUB Decode stage ADD Execute stage nCPI CPA CPB Instr fetch Instr fetch D[31:0] (ADD) CPA and CPB are ignored by the ARM7TDMI processor when it does not have a undefined or coprocessor instruction ...

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It is essential that any action taken by the coprocessor while it is busy-waiting is idempotent. This means that the actions taken by the coprocessor must not corrupt the state of the coprocessor, and must be repeatable with identical results. ...

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Coprocessor Interface 4.4.6 Coprocessor data operations Coprocessor data operations, CDP instructions, perform processing operations on the data held in the coprocessor register bank. No information is transferred between the ARM7TDMI processor and the coprocessor as a result of this operation. ...

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MCLK Fetch stage ADD SUB LDC n=4 Decode ADD stage Execute stage nCPI CPA CPB Instr fetch Instr fetch D[31:0] (ADD) (SUB) ARM DDI 0029G TST SUB LDC ADD SUB Instr fetch Instr fetch Instr fetch CP Data (LDC) (TST) ...

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Coprocessor Interface 4.5 Connecting coprocessors A coprocessor in an ARM7TDMI processor system must have 32-bit connections to: • the instruction stream from memory • data written by the core, MCR • data read by the core, MRC. The coprocessor can ...

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The logic for Figure 4 follows: 4.5.2 Connecting multiple coprocessors If you have multiple coprocessors in your system, connect the handshake signals as follows: nCPI CPA and CPB You must multiplex the output data from the coprocessors. Connecting ...

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Coprocessor Interface ARM core 4-14 CPA nCPI CPB CPA1 CPB1 Coprocessor 1 Figure 4-7 Connecting multiple coprocessors Copyright © 1994-2001. All rights reserved. CPAn CPBn CPB2 CPA2 Coprocessor Coprocessor 2 n ARM DDI 0029G ...

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If you are not using an external coprocessor If you are implementing a system that does not include any external coprocessors, you must tie both CPA and CPB HIGH. This indicates that no external coprocessors are present in the ...

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Coprocessor Interface 4.7 Undefined instructions Undefined instructions are treated by the ARM7TDMI processor as coprocessor instructions. All coprocessors must be absent, CPA and CPB must be HIGH, when an undefined instruction is presented. The ARM7TDMI processor takes the undefined instruction ...

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Privileged instructions The output signal nTRANS allows the implementation of coprocessors, or coprocessor instructions, that can only be accessed from privileged modes. The signal meanings are given in Table 4-4. If used, the nTRANS signal must be sampled at ...

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Coprocessor Interface 4-18 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G ...

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Chapter 5 Debug Interface This chapter describes the ARM7TDMI processor debug interface. It contains the following sections: • About the debug interface on page 5-2 • Debug systems on page 5-4 • Debug interface signals on page 5-6 • ARM7TDMI ...

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Debug Interface 5.1 About the debug interface The ARM7TDMI processor debug interface is based on IEEE Std. 1149.1 - 1990, Standard Test Access Port and Boundary-Scan Architecture. Refer to this standard for an explanation of the terms used in this ...

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When the ARM7TDMI processor is in the debug state, the core is clocked by DCLK under control of the TAP state machine and MCLK can free run. The selected clock is output on the signal ECLK for use by the ...

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Debug Interface 5.2 Debug systems Figure 5-1 shows a typical debug system using an ARM core. Debug host A debug system typically has three parts: • Debug host on page 5-4 • Protocol converter on page 5-4 • Debug target ...

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The ARM7TDMI processor has hardware extensions that ease debugging at the lowest level. The debug extensions: • allow you to halt program execution • examine and modify the core internal state of the core • view and modify the state ...

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Debug Interface 5.3 Debug interface signals There are three primary external signals associated with the debug interface: • BREAKPT and DBGRQ are system requests for the processor to enter debug state • DBGACK is used to indicate that the core ...

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BREAKPT Entry into debug state on breakpoint The ARM7TDMI core marks instructions as being breakpointed as they enter the instruction pipeline, but the core does not enter debug state until the instruction reaches the Execute stage. Breakpointed instructions are not ...

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Debug Interface • An exception occurs, causing the processor to flush the instruction pipeline and cancel the breakpoint. In normal circumstances, on exiting from an exception, the ARM7TDMI core branches back to the next instruction to be executed before the ...

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Action of the processor in debug state When the ARM7TDMI core enters debug state, the core forces nMREQ and SEQ to indicate internal cycles. This action allows the rest of the memory system to ignore the core and to ...

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Debug Interface 5.4 ARM7TDMI core clock domains The ARM7TDMI clocks are described in Clocks on page 5-2. This section describes: • Clock switch during debug on page 5-10 • Clock switch during test on page 5-11. 5.4.1 Clock switch during ...

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Clock switch during test When serial test patterns are being applied to the ARM7TDMI core through the JTAG interface, the processor must be clocked using DCLK, MCLK must be held LOW. Entry into test is less automatic than debug ...

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Debug Interface 5.5 Determining the core and system state When the core is in debug state, you can examine the core and system state by forcing the load and store multiples into the instruction pipeline. Before you can examine the ...

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About EmbeddedICE Logic The ARM7TDMI processor EmbeddedICE Logic provides integrated on-chip debug support for the ARM7TDMI core. The EmbeddedICE Logic is programmed serially using the ARM7TDMI processor TAP controller. Figure 5-5 illustrates the relationship between the core, EmbeddedICE Logic, ...

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Debug Interface The EmbeddedICE Logic comprises: • two real-time watchpoint units • two independent registers: — — • Debug Communications Channel (DCC). The debug control register and the debug status register provide overall control of EmbeddedICE operation. You can program ...

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Disabling EmbeddedICE The EmbeddedICE Logic is disabled by setting DBGEN LOW. Hard-wiring the DBGEN input LOW permanently disables the EmbeddedICE Logic. However, you must not rely upon this for system security. When DBGEN is LOW: • BREAKPT and DBGRQ ...

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Debug Interface 5.8 Debug Communications Channel The ARM7TDMI processor EmbeddedICE Logic contains a DCC to pass information between the target and the host debugger. This is implemented as coprocessor 14 (CP14). The DCC comprises: • a 32-bit communications data read ...

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The function of each register bit is as follows: Bits 31:28 Bits 27:2 Bit 1 Bit 0 From the point of view of the debugger, the registers are accessed through scan chain 2 in the usual way. From the point ...

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Debug Interface Sending a message to the debugger When the processor has to send a message to the debugger, it must check that the communications data write register is free for use by finding out if the W bit of ...

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DCC data write register is empty and available for use. These outputs are usually connected to the system interrupt controller, that drives the nIRQ and nFIQ ARM7TDMI processor inputs. ARM DDI 0029G Copyright © 1994-2001. All rights reserved. ...

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Debug Interface 5-20 Copyright © 1994-2001. All rights reserved. ARM DDI 0029G ...

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Chapter 6 Instruction Cycle Timings This chapter describes the ARM7TDMI processor instruction cycle operations. It contains the following sections: • About the instruction cycle timing tables on page 6-3 • Branch and branch with link on page 6-4 • Thumb ...

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Instruction Cycle Timings • Coprocessor register transfer, store to coprocessor on page 6-26 • Undefined instructions and coprocessor absent on page 6-27 • Unexecuted instructions on page 6-28 • Instruction speed summary on page 6-29. 6-2 Copyright © 1994-2001. All ...

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About the instruction cycle timing tables In the following tables: • nMREQ and SEQ, are pipelined up to one cycle ahead of the cycle to which they apply. They are shown in the cycle in which they appear and ...

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Instruction Cycle Timings 6.2 Branch and branch with link A branch instruction calculates the branch destination in the first cycle, while performing a prefetch from the current PC. This prefetch is done in all cases because, by the time the ...

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Thumb branch with link A Thumb Branch with Link operation consists of two consecutive Thumb instructions. Refer to the ARM Architecture Reference Manual for more information. The first instruction acts like a simple data operation to add the PC ...

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Instruction Cycle Timings 6.4 Branch and Exchange A Branch and Exchange (BX) operation takes three cycles and is similar to a branch. In the first cycle, the branch destination and the new core state are extracted from the register source, ...

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Data operations A data operation executes in a single datapath cycle unless a shift is determined by the contents of a register. A register is read onto the A bus, and a second register or the immediate field onto ...

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Instruction Cycle Timings Operation type normal dest=pc shift(Rs) shift(Rs) dest=pc The shifted register operations where the destination is the PC are not available in Thumb state. 6-8 Cycle Address MAS[1:0] 1 pc+2L i pc+3L 1 pc+ alu i ...

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Multiply and multiply accumulate The multiply instructions use special hardware that implements integer multiplication with early termination. All cycles except the first are internal The cycle timings are listed in the following tables: • multiply instruction cycle operations are ...

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Instruction Cycle Timings 6-10 Table 6-6 Multiply accumulate instruction cycle operations (continued) Cycle Address nRW MAS[1:0] m+1 pc+ m+2 pc+ pc+12 Table 6-7 Multiply long instruction cycle operations Cycle Address nRW MAS[1: ...

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The multiply accumulate, multiply long, and multiply accumulate long operations are not available in Thumb state. ARM DDI 0029G Note Copyright © 1994-2001. All rights reserved. Instruction Cycle Timings 6-11 ...

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Instruction Cycle Timings 6.7 Load register The first cycle of a load register instruction performs the address calculation. During the second cycle the data is fetched from memory and the base register modification is performed, if required. During the third ...

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Operation type Cycle Address normal 1 pc+2L 2 alu 3 pc+3L pc+3L dest=pc 1 pc+8 2 alu 3 pc+12 4 pc’ 5 pc’+4 pc’+8 Operations where the destination is the PC are not available in Thumb state. ARM DDI 0029G ...

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Instruction Cycle Timings 6.8 Store register The first cycle of a store register instruction is similar to the first cycle of load register instruction. During the second cycle the base modification is performed, and at the same time the data ...

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Load multiple registers The first cycle of the LDM instruction is used to calculate the address of the first word to be transferred, while performing a prefetch from memory. The second cycle fetches the first word, and performs the ...

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Instruction Cycle Timings Destination registers Single register dest=pc n registers (n>1) n registers (n>1) including pc 6-16 Table 6-12 Load multiple registers instruction cycle operations (continued) Cycle Address MAS[1:0] 1 pc+ alu 2 3 pc+ pc’ ...

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Store multiple registers The store multiple instruction proceeds very much as load multiple instruction, without the final cycle. The abort handling is much more straightforward as there is no wholesale overwriting of registers. The cycle timings are listed in ...

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Instruction Cycle Timings 6.11 Data swap This is similar to the load and store register instructions, but the actual swap takes place in the second and third cycles. In the second cycle, the data is fetched from external memory. In ...

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Software interrupt and exception entry Exceptions (including software interrupts) force the particular value and cause the instruction pipeline to be refilled. During the first cycle the forced address is constructed, and a mode change can take ...

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Instruction Cycle Timings 6.13 Coprocessor data operation A coprocessor data operation is a request from the core for the coprocessor to initiate some action. The action does not have to be completed for some time, but the coprocessor must commit ...

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Coprocessor data transfer from memory to coprocessor For coprocessor transfer instructions from memory the coprocessor must commit to the transfer only when it is ready to accept the data. When CPB goes LOW, the processor produces the addresses and ...

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Instruction Cycle Timings Table 6-17 Coprocessor data transfer instruction cycle operations (continued) CP register Cycles Address status n registers 1 pc+8 (n>1) 2 pc+8 not ready • pc+8 b pc+8 b+1 alu • alu+• n+b alu+• n+b+1 alu+• pc+12 Coprocessor ...

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Coprocessor data transfer from coprocessor to memory The ARM7TDMI processor controls these instructions in the same way as for memory to coprocessor transfers, with the exception that the nRW line is inverted during the transfer cycle. The cycle timings ...

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Instruction Cycle Timings Table 6-18 coprocessor data transfer instruction cycle operations (continued) CP register Cycle Address status n registers 1 pc+8 (n>1) 2 pc+8 not ready • pc+8 b pc+8 b+1 alu • alu+• n+b alu+• n+b+1 alu+• pc+12 Coprocessor ...

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Coprocessor register transfer, load from coprocessor The busy-wait cycles are similar to those described in Coprocessor data transfer from memory to coprocessor on page 6-21, but the transfer is limited to one word, and the ARM7TDMI core puts the ...

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Instruction Cycle Timings 6.17 Coprocessor register transfer, store to coprocessor This is the same as described in Coprocessor register transfer, load from coprocessor on page 6-25, except that the last cycle is omitted. The cycle timings are listed in Table ...

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Undefined instructions and coprocessor absent When the processor attempts to execute an instruction that neither it nor a coprocessor can perform (including all undefined instructions) this causes the processor to take the undefined instruction trap. Cycle timings are listed ...

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Instruction Cycle Timings 6.19 Unexecuted instructions Any instruction whose condition code is not met does not execute and adds one cycle to the execution time of the code segment in which it is embedded (see Table 6-22). 6-28 Table 6-22 ...

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Instruction speed summary Due to the pipelined architecture of the CPU, instructions overlap considerably typical cycle, one instruction can be using the data path while the next is being decoded and the one after that is being ...

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Instruction Cycle Timings 6-30 Table 6-23 ARM instruction speed summary (continued) Instruction MULL MLAL CDP LDC, STC MCR MRC Copyright © 1994-2001. All rights reserved. Cycle count Additional S+(m+1)I - S+(m+2)I - S+bI - (n-1)S+2N+bI - N+bI+C - S+(b+1)I+C - ...

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Chapter 7 AC and DC Parameters This chapter gives the AC timing parameters of the ARM7TDMI core. It contains the following sections: • Timing diagram information on page 7-3 • General timing on page 7-4 • Address bus enable control ...

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AC and DC Parameters • Test clock and external clock timing on page 7-21 • Memory clock timing on page 7-22 • Boundary scan general timing on page 7-23 • Reset period timing on page 7-24 • Output enable and ...

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Timing diagram information Each timing diagram in this chapter is provided with a table that shows the timing parameters. In the tables: • the letter f at the end of a signal name indicates the falling edge • the ...

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AC and DC Parameters 7.2 General timing Figure 7-1 shows the ARM7TDMI general timing. The timing parameters used in Figure 7-1 are listed in Table 7-1 on page 7-5. MCLK ECLK nMREQ nEXEC A[31:0] nRW MAS[1:0] LOCK nM[4:0] nTRANS nOPC ...

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In Figure 7-1 on page 7-4, nWAIT, APE, ALE, and ABE are all HIGH during the cycle shown ECLK. ARM DDI 0029G Note is the delay, on either edge (whichever is greater), from the edge of MCLK cdel ...

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AC and DC Parameters 7.3 Address bus enable control Figure 7-2 shows the ARM7TDMI ABE control timing. The timing parameters used in Figure 7-2 are listed in Table 7-2. MCLK ABE A[31:0] nRW LOCK nOPC nTRANS MAS[1:0] 7-6 T abz ...

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Bidirectional data write cycle Figure 7-3 shows the ARM7TDMI processor bidirectional data write cycle timing. The timing parameters used in Figure 7-3 are listed in Table 7-3. MCLK nENOUT D[31:0] In Figure 7-3 DBE is HIGH and nENIN is ...

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AC and DC Parameters 7.5 Bidirectional data read cycle Figure 7-4 shows the ARM7TDMI processor bidirectional data read cycle timing. The timing parameters used in Figure 7-4 are listed in Table 7-4. MCLK nENOUT D[31:0] BL[3:0] In Figure 7-4, DBE ...

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Data bus control Figure 7-5 shows the ARM7TDMI data bus control timing. The timing parameters used in Figure 7-5 are listed in Table 7-5. MCLK nENOUT DBE D[31:0] nENIN The cycle shown in Figure 7 data write ...

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AC and DC Parameters 7.7 Output 3-state timing Figure 7-6 shows the ARM7TDMI processor output 3-state timing. The timing parameters used in Figure 7-6 are listed in Table 7-6. MCLK TBE A[31:0] D[31:0] nRW LOCK nOPC nTRANS MAS[1:0] 7-10 T ...

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Unidirectional data write cycle timing Figure 7-7 shows the ARM7TDMI processor unidirectional data write cycle timing. The timing parameters used in Figure 7-6 are listed in Table 7-6. MCLK nENOUT DOUT[31:0] ARM DDI 0029G T nen T dohu T ...

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AC and DC Parameters 7.9 Unidirectional data read cycle timing Figure 7-8 shows the ARM7TDMI processor unidirectional data read cycle timing. The timing parameters used in Figure 7-7 are listed in Table 7-7. MCLK nENOUT DIN[31:0] BL[3:0] 7-12 T nen ...

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Configuration pin timing Figure 7-9 shows the ARM7TDMI processor configuration pin timing. The timing parameters used in Figure 7-9 are listed in Table 7-9. MCLK BIGEND ISYNC ARM DDI 0029G T cth T cts T cts T cth Table ...

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AC and DC Parameters 7.11 Coprocessor timing Figure 7-10 shows the ARM7TDMI processor coprocessor timing. The timing parameters used in Figure 7-10 are listed in Table 7-10. MCLK nCPI CPA CPB nMREQ SEQ In Figure 7-10, usually nMREQ and SEQ ...

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Exception timing Figure 7-11 shows the ARM7TDMI processor exception timing. The timing parameters used in Figure 7-11 are listed in Table 7-11. MCLK ABORT nFIQ nIRQ nRESET In Figure 7-11, to guarantee recognition of the asynchronous interrupt (ISYNC=0) or ...

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AC and DC Parameters 7.13 Synchronous interrupt timing Figure 7-12 shows the ARM7TDMI processor synchronous interrupt timing. The timing parameters used in Figure 7-12 are listed in Table 7-12. MCLK nFIQ nIRQ Symbol T sih T sis 7-16 Table 7-12 ...

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Debug timing Figure 7-13 shows the ARM7TDMI processor synchronous interrupt timing. The timing parameters used in Figure 7-13 are listed in Table 7-13. MCLK DBGACK BREAKPT DBGRQ EXTERN[1] DBGRQI RANGEOUT0 RANGEOUT1 Symbol T brkh T brks T dbgd T ...

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AC and DC Parameters Symbol T rgh T rqh T rqs 7-18 Table 7-13 Debug timing parameters (continued) Parameter RANGEOUT0, RANGEOUT1 hold time from MCLKf DBGRQ guaranteed non-recognition time DBGRQ set up time to MCLKr for guaranteed recognition Copyright © ...

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Debug communications channel output timing Figure 7-14 shows the ARM7TDMI processor DCC output timing. The timing parameter used in Figure 7-14 is listed in Table 7-14. ARM DDI 0029G MCLK COMMTX COMMRX Table 7-14 DCC output timing parameters Symbol ...

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AC and DC Parameters 7.16 Breakpoint timing Figure 7-15 shows the ARM7TDMI processor synchronous interrupt timing. The timing parameter used in Figure 7-12 is listed in Table 7-12. MCLK BREAKPT nCPI nEXEC nMREQ SEQ In Figure 7-15, BREAKPT changing in ...

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Test clock and external clock timing Figure 7-16 shows the ARM7TDMI processor test clock and external clock timing. The timing parameter used in Figure 7-16 is listed in Table 7-16. TCK ECLK In Figure 7-16 TCK to ...

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AC and DC Parameters 7.18 Memory clock timing Figure 7-17 shows the ARM7TDMI processor memory clock timing. The timing parameters used in Figure 7-17 are listed in Table 7-17. In Figure 7-17, the core is not clocked by the HIGH ...

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Boundary scan general timing Figure 7-18 shows the ARM7TDMI processor boundary scan general timing. The timing parameters used in Figure 7-18 are listed in Table 7-18. ARM DDI 0029G TCK T bscl TMS TDI T T bsoh TDO T ...

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AC and DC Parameters 7.20 Reset period timing Figure 7-19 shows the ARM7TDMI reset period timing. The timing parameters used in Figure 7-19 are listed in Table 7-19. Symbol Parameter T nTRST reset period bsr T nRESETf to D[31:0], DBGACK, ...

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Output enable and disable times Figure 7-20 shows the output enable and disable times due to a HIGHZ TAP instruction. Figure 7-21 shows the output enable and disable times due to data scanning.The timing parameters used in Figure 7-20 ...

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AC and DC Parameters 7.22 Address latch enable control Figure 7-22 shows the ARM7TDMI reset period timing. The timing parameters used in Figure 7-22 are listed in Table 7-21. In Figure 7-22, T address in phase 2. If ALE is ...

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Address pipeline control timing Figure 7-23 shows the ARM7TDMI APE control timing. The timing parameters used in Figure 7-23 are listed in Table 7-22. MCLK APE A[31:0] nRW LOCK nOPC nTRANS MAS[1:0] ARM DDI 0029G T T aph aps ...

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AC and DC Parameters 7.24 Notes on AC Parameters Table 7-23 lists the AC timing parameters in alphabetical order. Contact your supplier for AC timing parameter values. In Table 7-23: • the letter f at the end of a signal ...

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