SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet
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Technical Reference Manual Copyright © 1999, 2000 ARM Limited. All rights reserved. ARM DDI 0165B ARM9E-S (Rev 1) ...
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ARM9E-S Technical Reference Manual Copyright © 1999, 2000 ARM Limited. All rights reserved. Release Information Date 16th December 1999 12th September 2000 Proprietary Notice ARM, The ARM Powered logo, Thumb, and StrongARM are registered trademarks of ARM Limited. The ARM ...
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Contents ARM9E-S Technical Reference Manual Preface Chapter 1 Introduction 1.1 1.2 1.3 1.4 Chapter 2 Programmer’s Model 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 ARM DDI 0165B About this document .................................................................................... xvi Further reading ............................................................................................ xix Feedback ...................................................................................................... ...
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Contents Chapter 3 Device Reset 3.1 3.2 3.3 Chapter 4 Memory Interface 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 Chapter 5 Interrupts 5.1 5.2 5.3 5.4 Chapter 6 ARM9E-S Coprocessor Interface 6.1 6.2 6.3 6.4 ...
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Chapter 7 Debug Interface and EmbeddedICE-RT 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Chapter 8 Instruction Cycle Times 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 ...
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Contents Appendix A Signal Descriptions A.1 A.2 A.3 A.4 A.5 A.6 Appendix B Differences Between the ARM9E-S and the ARM9TDMI B.1 B.2 B.3 B.4 B.5 Appendix C Debug in depth C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 ...
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List of Tables ARM9E-S Technical Reference Manual Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12 Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table ...
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Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 4-11 Table 4-12 Table 4-13 Table 4-14 Table 4-15 Table 4-16 Table 6-1 Table 6-2 Table 7-1 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 ...
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Table 8-33 Table 8-34 Table 8-35 Table 8-36 Table 9-1 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table B-1 Table C-1 Table C-2 Table C-3 Table C-4 Table C-5 Table C-6 Table C-7 Table C-8 ...
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Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0165B ...
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List of Figures ARM9E-S Technical Reference Manual Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure ...
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Figure 4-12 Figure 4-13 Figure 5-1 Figure 5-2 Figure 5-3 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Figure 6-10 Figure 6-11 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 ...
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Preface This preface introduces the ARM9E-S and its reference documentation. It contains the following sections: • About this document on page xiv • Further reading on page xvii • Feedback on page xviii. ARM DDI 0165B Copyright © 2000 ARM ...
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Preface About this document This document is the technical reference manual for the ARM9E-S. Intended audience This document has been written for hardware and software engineers who want to design or develop products based upon the ARM9E-S family of processors. ...
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Chapter 8 Instruction Cycle Times Chapter 9 AC Parameters Appendix A Signal Descriptions Appendix B Differences Appendix C Debug in depth Typographical conventions The following typographical conventions are used in this book: bold italic typewriter typewriter typewriter italic typewriter bold ...
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Preface Timing diagram conventions This manual contains a number of timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labeled when they occur. Therefore, you must not attach any additional meaning unless specifically ...
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Further reading This section lists publications by ARM Limited, and by third parties. If you would like further information on ARM products you have questions not answered by this document, please contact http://www.arm.com ARM publications This document contains ...
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Preface Feedback ARM Limited welcomes feedback both on the ARM9E-S, and on the documentation. Feedback on the ARM9E-S If you have any comments or suggestions about this product, please contact your supplier giving: • the product name • a concise ...
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Chapter 1- Introduction This chapter introduces the ARM9E-S. It contains the following sections: • About the ARM9E-S on page 1-2 • ARM9E-S architecture on page 1-5 • ARM9E-S block, core, and interface diagrams on page 1-7 • ARM9E-S instruction set ...
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Introduction 1.1 About the ARM9E-S The ARM9E member of the ARM family of general-purpose 32-bit microprocessors. The ARM family offers high performance for very low power consumption and gate count. The ARM architecture is based on Reduced Instruction ...
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ARM The program counter points to the instruction being fetched rather than to the instruction being executed. During normal operation: • ...
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Introduction Typical pipeline operation is shown in Figure 1-2. CLK IA[31:1], InMREQ, ISEQ INSTR[31:0] DA[31:0], DnMREQ, DSEQ, DMORE WDATA[31:0] RDATA[31:0] 1.1.2 Memory access The ARM9E-S has a Harvard architecture. This features separate address and data buses for both the 32-bit ...
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ARM9E-S architecture The ARM9E-S processor has two instruction sets: • the 32-bit ARM instruction set used in ARM state • the 16-bit Thumb instruction set used in Thumb state. The ARM9E implementation of the ARMv5TE architecture. For ...
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Introduction Thumb therefore offers a long branch range, powerful arithmetic operations, and a large address space. Thumb code is typically 65% of the size of the ARM code, and provides 160% of the performance of ARM code when running on ...
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ARM9E-S block, core, and interface diagrams The ARM9E-S architecture, core, and interface diagrams are shown in the following figures: • the ARM9E-S block diagram is shown in Figure 1-3 • the ARM9E-S core diagram is shown in Figure 1-4 ...
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Introduction IA[31:1] IAScan IAreg Exception vectors PSRRD[31:0] MulResultMe[31:0] SAT ALUOutEx[31:0] 1-8 Incrementer ResultMe[31:0] Register bank plus PSR program counter A[31:0] Imm B[31:0] Amux Bmux Multiplier AData[..] BData[..] Shift ACC Byte/ word repl. SAT(x2) Shifter CLZ ALU DINC DAreg DAScan DA[31:0] ...
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Clock Interrupts Miscellaneous configuration Instruction memory interface Debug ARM DDI 0165B CLK CLKEN CORECLKENOUT CORECLKENIN nIRQ nFIQ nRESET CFGHIVECS CFGDISLTBIT CFGBIGEND IA[31:1] INSTR[31:0] IABORT InMREQ ISEQ ITBIT InTRANS InM[4:0] DBGIEBKPT DBGDEWPT EDBGRQ DBGACK DBGEXT[1:0] DBGEN DBGRNG[1:0] DBGCOMMRX DBGCOMMTX DBGRQI DBGINSTREXEC ...
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Introduction 1.4 ARM9E-S instruction set summary This section provides a summary of the ARM and Thumb instruction sets: • ARM instruction set summary on page 1-12 • Thumb instruction set summary on page 1-21. A key to the instruction set ...
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Symbol <reglist> ARM DDI 0165B Description A comma-separated list of registers, enclosed in braces ({ and }). Selects HIGH or LOW 16 bits of register Rm. T selects the HIGH 16 bits top) B selects the ...
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Introduction 1.4.1 ARM instruction set summary The ARM instruction set summary is given in Table 1-2. Operation Move Move Move NOT Move SPSR to register Move CPSR to register Move register to SPSR Move register to CPSR Move immediate to ...
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Operation Saturating add with double Saturating subtract Saturating subtract with double Multiply 16x16 Multiply accumulate 16x16+32 Multiply 32x16 Multiply accumulate 32x16+32 Multiply signed accumulate long 16x16+64 Count leading zeros Logical Test Test equivalence AND XOR OR Bit clear Branch Branch ...
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Introduction Operation Byte signed Halfword Halfword signed Multiple block Stack operations data operations Increment before Increment after Decrement before Decrement after Stack operations and restore CPSR User registers Load double Store Word Word with User mode privilege Byte Byte with ...
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Operation Swap Word Byte Coprocessors Data operations Move to ARM reg from coproc Move to coproc from ARM reg Move double to ARM reg from coproc Move double to coproc from ARM reg Load Store Software interrupt Software breakpoint ARM ...
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Introduction Addressing mode 2 is summarized in Table 1-3. Operation Immediate offset Register offset Scaled register offset Pre-indexed offset Immediate Register Scaled register Post-indexed offset Immediate Register Scaled register 1-16 Assembler [Rn, #+/-12bit_Offset] [Rn, +/-Rm] [Rn, +/-Rm, LSL #5bit_shift_imm] [Rn, ...
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Addressing mode 2 (privileged) is summarized in Table 1-4. Operation Immediate offset Register offset Scaled register offset Post-indexed offset Immediate Register Scaled register ARM DDI 0165B Assembler [Rn, #+/-12bit_Offset] [Rn, +/-Rm] [Rn, +/-Rm, LSL #5bit_shift_imm] [Rn, +/-Rm, LSR #5bit_shift_imm] [Rn, ...
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Introduction Addressing mode 3 is summarized in Table 1-5. Operation Immediate offset Pre-indexed Post-indexed Register offset Pre-indexed Post-indexed Addressing mode 4 (load) is summarized in Table 1-6. Addressing mode IA Increment after IB Increment before DA Decrement after DB Decrement ...
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Addressing mode 5 (load) is summarized in Table 1-8. Operation Immediate offset Pre-indexed Post-indexed Oprnd2 is summarized in Table 1-9. Operation Immediate value Logical shift left Logical shift right Arithmetic shift right Rotate right Register Logical shift left Logical shift ...
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Introduction Fields are summarized in Table 1-10. Condition fields are summarized in Table 1-11. 1-20 Copyright © 2000 ARM Limited. All rights reserved. Table 1-10 Fields Suffix Sets Control field mask bit (bit 0) _c Extension field mask bit (bit ...
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Thumb instruction set summary The Thumb instruction set summary is given in Table 1-12. Operation Move Arithmetic ARM DDI 0165B Immediate High to Low Low to High High to High Add Add Low and Low Add High to Low ...
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Introduction Operation Logical Shift/Rotate Branch 1-22 Table 1-12 Thumb instruction set summary (continued) Compare Immediate AND XOR OR Bit clear Move NOT Test bits Logical shift left Logical shift right Arithmetic shift right Rotate right Conditional If Z set If ...
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Operation Branch and exchange Branch, link and exchange Load ARM DDI 0165B Table 1-12 Thumb instruction set summary (continued set and V clear clear and V set If Z clear, and N and V set, ...
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Introduction Operation Store Push/Pop Software interrupt Software breakpoint 1-24 Table 1-12 Thumb instruction set summary (continued) Address Using PC Using SP Multiple With immediate offset Word Halfword Byte With register offset Word Halfword Byte SP-relative Multiple Push registers onto stack ...
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Chapter 2- Programmer’s Model This chapter describes the ARM9E-S programmer’s model. It contains the following sections: • About the programmer’s model on page 2-2 • Processor operating states on page 2-3 • Memory formats on page 2-4 • Instruction length ...
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Programmer’s Model 2.1 About the programmer’s model The ARM9E-S processor core implements ARMv5TE architecture. This includes the 32-bit ARM instruction set and the 16-bit Thumb instruction set. For details of both the ARM and Thumb instruction sets, refer to the ...
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Processor operating states The ARM9E-S has two operating states: ARM state Thumb state In Thumb state, the Program Counter (PC) uses bit 1 to select between alternate halfwords. Transition between ARM and Thumb states does not affect the processor ...
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Programmer’s Model 2.3 Memory formats The ARM9E-S views memory as a linear collection of bytes numbered in ascending order from zero. Bytes hold the first stored word, and bytes hold the second stored word, ...
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ARM DDI 0165B Bit Higher address Lower address • Least significant byte is at lowest address • Word is addressed by byte address of least significant byte Figure 2-2 Little-endian addresses ...
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Programmer’s Model 2.4 Instruction length Instructions are either: • 32 bits long (in ARM state) • 16 bits long (in Thumb state). 2-6 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0165B ...
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Data types The ARM9E-S supports the following data types: • word (32-bit) • halfword (16-bit) • byte (8-bit). You must align these as follows: • word quantities must be aligned to four-byte boundaries • halfword quantities must be aligned ...
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Programmer’s Model 2.6 Operating modes The ARM9E-S has seven modes of operation: • User mode is the usual ARM program execution state, and is used for executing most application programs. • Fast interrupt (FIQ) mode is used for handling fast ...
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Registers The ARM9E-S has a total of 37 registers: • 31 general-purpose 32-bit registers • 6 32-bit status registers. These registers are not all accessible at the same time. The processor state and operating mode determine which registers are ...
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Programmer’s Model Banked registers have a mode identifier that indicates which User mode register they are mapped to. These mode identifiers are shown in Table 2-1. FIQ mode has seven banked registers mapped to r8–r14 (r8_fiq–r14_fiq result many ...
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Figure 2-3 shows the ARM state registers. ARM state general registers and program counter System and User FIQ r8_fiq r9 r9_fiq r10 r10_fiq ...
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Programmer’s Model 2.7.2 The Thumb state register set The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • eight general registers, r0–r7 (for details of high register access in Thumb ...
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Thumb state general registers and program counter System and User FIQ SP_fiq LR LR_fiq PC PC CPSR CPSR SPSR_fiq Indicates that the normal ...
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Programmer’s Model 2.7.3 The relationship between ARM state and Thumb state registers The Thumb state registers relate to the ARM state registers in the following way: • Thumb state r0–r7 and ARM state r0–r7 are identical. • Thumb state CPSR ...
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Accessing high registers in Thumb state In Thumb state, the high registers (r8–r15) are not part of the standard register set. With assembly language programming you have limited access to them, but can use them for fast temporary storage. ...
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Programmer’s Model 2.8 The program status registers The ARM9E-S contains a CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling ...
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The Q flag The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions: • QADD • QDADD • QSUB • QDSUB • SMLAxy • SMLAWy The Q flag is sticky in that, once set by ...
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Programmer’s Model The T bit reflects the operating state: • when the T bit is set, the processor is executing in Thumb state • when the T bit is clear, the processor is executing in ARM state. The operating state ...
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Reserved bits The remaining bits in the PSRs are unused, but are reserved. When changing a PSR flag or control bits, make sure that these reserved bits are not altered. You must ensure that your program does not rely ...
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Programmer’s Model 2.9 Exceptions Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example, to service an interrupt from a peripheral. Before attempting to handle an exception, the ARM9E-S preserves the current processor state ...
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Entering an exception When handling an exception the ARM9E-S: 1. Preserves the address of the next instruction in the appropriate LR. When the exception entry is from: • • The exception handler does not need to determine the state ...
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Programmer’s Model 2.9.4 Reset When the nRESET signal is driven LOW a reset occurs, and the ARM9E-S abandons the executing instruction. When nRESET is driven HIGH again the ARM9E-S: 1. Forces CPSR[4:0] to b10011 (Supervisor mode), sets the I and ...
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Irrespective of whether exception entry is from ARM state or Thumb state, an IRQ handler returns from the interrupt by executing: SUBS PC,R14_irq,#4 You can disable IRQ exceptions within a privileged mode by setting the CPSR I flag. When the ...
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Programmer’s Model The ARM9E-S implements the base restored Data Abort model, which differs from the base updated Data Abort model implemented by the ARM7TDMI-S. The difference in the Data Abort model affects only a very small section of operating system ...
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Undefined instruction When an instruction is encountered that neither the ARM9E-S, nor any coprocessor in the system can handle, the ARM9E-S takes the undefined instruction trap. Software can use this mechanism to extend the ARM instruction set by emulating ...
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Programmer’s Model 2.9.11 Exception vectors You can configure the location of the exception vector addresses using the input CFGHIVECS, as shown in Table 2-4. Table 2-5 shows the exception vector addresses and entry conditions for the different exception types. Exception ...
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Exception priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: 1. Reset (highest priority). 2. Data Abort. 3. FIQ. 4. IRQ. 5. Prefetch Abort. 6. BKPT, undefined ...
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Programmer’s Model 2-28 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0165B ...
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Chapter 3- Device Reset This chapter describes the ARM9E-S reset behavior. It contains the following sections: • About device reset on page 3-2 • Reset modes on page 3-3 • ARM9E-S behavior on exit from reset on page 3-5. ARM ...
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Device Reset 3.1 About device reset This section describes the ARM9E-S reset signals and how you must use them for correct operation of the device. The ARM9E-S has two reset inputs: nRESET DBGnTRST The DBGnTRST signal is the debug logic ...
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Reset modes Two reset signals are present in the ARM9E-S design to enable you to reset different parts of the design independently. A description of the reset signaling combinations and possible applications is shown in Table 3-1. Reset mode ...
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Device Reset 3.2.2 CPU reset A CPU or warm reset initializes the majority of the ARM9E-S CPU, excluding the ARM9E-S TAP controller and the EmbeddedICE-RT unit. CPU reset is typically used for resetting a system that has been operating for ...
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ARM9E-S behavior on exit from reset When nRESET is driven LOW, the currently executing instruction terminates abnormally. InMREQ, ISEQ, DnMREQ, DSEQ, and DMORE change asynchronously to indicate an internal cycle. When nRESET is driven HIGH, the ARM9E-S starts requesting ...
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Device Reset 3-6 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0165B ...
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Chapter 4- Memory Interface This chapter describes the ARM9E-S memory interface. It contains the following sections: • About the memory interface on page 4-2 • Instruction interface on page 4-3 • Instruction interface addressing signals on page 4-4 • Instruction ...
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Memory Interface 4.1 About the memory interface The ARM9E-S has a Harvard bus architecture with separate instruction and data interfaces. This allows concurrent instruction and data accesses, and greatly reduces the Cycles Per Instruction (CPI) of the processor. For optimal ...
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Instruction interface The ARM9E-S requests instructions for execution using the instruction memory interface. A new instruction is fetched over the instruction bus whenever an instruction enters the Execute stage of the pipeline. Instruction fetches take place in the Fetch ...
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Memory Interface 4.3 Instruction interface addressing signals The address class signals for the instruction memory interface are: • IA[31:1] • ITBIT • InTRANS on page 4-5 • InM[4:0] on page 4-5. 4.3.1 IA[31:1] IA[31:1] is the 31-bit address bus that ...
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InTRANS The InTRANS signal encodes information about the transfer. A memory management unit uses this signal to determine if an access is from a privileged mode. Therefore, you can use this signal to implement an access permission scheme. The ...
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Memory Interface 4.4 Instruction interface data timed signals The data timed signals for the instruction memory interface are: • INSTR[31:0] • IABORT. 4.4.1 INSTR[31:0] INSTR[31:0] is the read data bus, and is used by the ARM9E-S to fetch opcodes. The ...
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Endian effects for instruction fetches The ARM9E-S performs 32-bit or 16-bit instruction fetches depending on whether the processor is in ARM or Thumb state. The processor state can be determined externally by the value of the ITBIT signal. When ...
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Memory Interface 4.6 Instruction interface cycle types The ARM9E-S instruction interface is pipelined. The address class signals and the memory request signals are broadcast in the bus cycle ahead of the bus cycle to which they refer. This gives the ...
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The ARM9E-S instruction interface has three types of memory cycle: Nonsequential cycle Sequential cycle Internal cycle 4.6.1 Instruction interface, nonsequential cycles A nonsequential instruction fetch is the simplest form of an ARM9E-S instruction interface cycle, and occurs when the ARM9E-S ...
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Memory Interface 4.6.2 Instruction interface, sequential cycles Sequential instruction fetches are used to perform burst transfers on the bus. This information can be used to optimize the design of a memory controller interfacing to a burst memory device, such as ...
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Instruction interface, internal cycles During an internal cycle, the ARM9E-S does not require an instruction fetch, because an internal function is being performed, and no useful prefetching can be performed at the same time. Where possible the ARM9E-S broadcasts ...
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Memory Interface CLK Address class signals InMREQ, ISEQ INSTR[31:0] There is an exception to the merged I-S behavior in the case of a coprocessor 15 In this case the IA bus is used to transmit data to CP15 (see Coprocessor ...
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Data interface The ARM9E-S requests data using the data memory interface. Data transfers take place in the Memory stage of the pipeline. The operation of the data interface is very similar to the instruction interface. 4.7.1 Data interface signals ...
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Memory Interface Each of these signal groups shares a common timing relationship to the bus interface cycle. All signals in the ARM9E-S data interface are generated from, or sampled by the rising edge of CLK. You can extend bus cycles ...
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Data interface addressing signals The address class signals are: • DA[31:0] • DnRW • DMAS[1:0] on page 4-16 • DnTRANS on page 4-16 • DLOCK on page 4-17 • DnM[4:0] on page 4-17. 4.8.1 DA[31:0] DA[31:0] is the 32-bit ...
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Memory Interface 4.8.3 DMAS[1:0] The DMAS[1:0] bus encodes the size of the transfer. The ARM9E-S can transfer word, halfword, and byte quantities. This is encoded on DMAS[1:0] as shown in Table 4-8. The size of transfer does not change during ...
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DLOCK DLOCK indicates to an arbiter that an atomic operation is being performed on the bus. DLOCK is normally LOW, but is set HIGH to indicate that a is being performed. These instructions perform an atomic read/write operation, and ...
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Memory Interface 4.9 Data interface data timed signals The data timed signals are: • WDATA[31:0] • RDATA[31:0] • DABORT. 4.9.1 WDATA[31:0] WDATA[31:0] is the write data bus. All data written out from the ARM9E-S is broadcast on this bus. Data ...
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This DABORT to DnMREQ, DSEQ, and DMORE path has been removed from the ARM9E-S design because: • a combinational input to output path is undesirable in an ASIC design flow • the path is critical in ARM9TDMI. Due to this ...
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Memory Interface Figure 4-6 shows the ARM9E-S behavior for an aborted STR instruction followed by an LDM instruction. While the STR instruction is canceled, a memory request is made in the first cycle of the LDM before the Data Abort ...
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Byte and halfword accesses The ARM9E-S indicates the size of a transfer using the DMAS[1:0] signals. These are encoded as shown in Table 4-10. All writable memory in an ARM9E-S based system must support the writing of individual bytes ...
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Memory Interface The fields extracted by the ARM9E-S are shown in Table 4-12. DMAS[1:0] 10 When performing a word load, the ARM9E-S can rotate the data returned internally if the address used is unaligned. Refer to the ARM Architectural Reference ...
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Writes When the ARM9E-S performs a byte or halfword write, the data being written is replicated across the bus, as illustrated in Figure 4-7. The memory system can use the most convenient copy of the data. A writable memory system ...
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Memory Interface 4.10 Data interface cycle types The ARM9E-S data interface is pipelined, and so the address class signals and the memory request signals are broadcast in the bus cycle ahead of the bus cycle to which they refer. This ...
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A memory controller for the ARM9E-S must commit to a data memory access only cycle cycle. The ARM9E-S data interface has four types of memory cycle: Nonsequential cycle Sequential cycle Internal cycle Coprocessor register ...
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Memory Interface The ARM9E-S can perform back to back, nonsequential memory cycles. This happens, for example, when an succession, as shown in Figure 4-10 on page 4-27. 4-26 CLK Address class signals DnMREQ, DSEQ, DMORE WDATA[31:0] (Write) RDATA[31:0] (Read) Figure ...
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CLK Address class signals DnRW DnMREQ, DSEQ, DMORE WDATA[31:0] (Write) RDATA[31:0] (Read) If you are designing a memory controller for the ARM9E-S, and your memory system is unable to cope with this case, use the CLKEN signal to extend the ...
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Memory Interface The types of bursts are shown in Table 4-16. Burst type Word read Word write All accesses in a burst are of the same width, direction, and protection type. For more details, see Instruction interface addressing signals on ...
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Data interface, internal cycles During an internal cycle, the ARM9E-S does not require a memory access internal function is being performed. 4.10.4 Data interface, merged I-S cycles The ARM9E-S does not perform merged I-S cycles on the ...
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Memory Interface 4.11 Endian effects for data transfers The ARM9E-S supports 32-bit, 16-bit, and 8-bit data memory access sizes. The endian configuration of the processor, set by CFGBIGEND, affects only nonword transfers (16-bit and 8-bit transfers). 4.11.1 Writes For data ...
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Use of CLKEN to control bus cycles The pipelined nature of the ARM9E-S bus interface means that there is a distinction between clock cycles and bus cycles. You can use CLKEN to stretch a bus cycle, so that it ...
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Memory Interface during a waited cycle. In addition, the ARM9E-S can alter the request for a subsequent memory cycle during a waited (CLKEN LOW) cycle. See Withdrawal of memory requests in waited cycles. 4.12.1 Withdrawal of memory requests in waited ...
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Chapter 5- Interrupts This chapter describes the ARM9E-S interrupt behavior. It contains the following sections: • About interrupts on page 5-2 • Hardware interface on page 5-3 • Maximum interrupt latency on page 5-7 • Minimum interrupt latency on page ...
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Interrupts 5.1 About interrupts The ARM9E-S provides a two-level, fixed-priority asynchronous hardware interrupt scheme. Asynchronous is used here to mean asynchronous to the instruction flow, not to the processor clock (CLK). Refer to Chapter 9 AC Parameters for details on ...
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Hardware interface The hardware interrupt is described under the following headings: • Generating an interrupt • Synchronization • Re-enabling interrupts after an interrupt exception • Interrupt registers on page 5-5. 5.2.1 Generating an interrupt You can make the ARM9E-S ...
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Interrupts nFIQ or nIRQ) typically does not take effect until after the Memory stage of that instruction. The instruction that re-enables interrupts on the ARM9E-S can cause the ARM9E sensitive to interrupts as early as the Execute stage ...
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Example approaches are: • Analyze the system and ensure enough instructions separate the instruction that removes the interrupt and the instruction that re-enables interrupts on the ARM9E-S. • Have a software polling mechanism that reads back a status bit from ...
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Interrupts The system shown in Figure 5-3 combines CLK stopping and CLKEN waiting for best power and interrupt latency performance. 5-6 Figure 5-3 Using CLK and CLKEN for best interrupt latency Copyright © 2000 ARM Limited. All rights reserved. ARM ...
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Maximum interrupt latency The processor samples the interrupt input pins on the rising-edge of the system clock, CLK. The sampled signal is examined and can cause an interrupt in the following cases: • Whenever a new instruction is scheduled ...
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Interrupts 5.4 Minimum interrupt latency The minimum latency for FIQ or IRQ is the shortest time the request can be sampled by the input register (one cycle), plus the exception entry time (three cycles). The first interrupt instruction enters the ...
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Chapter 6- ARM9E-S Coprocessor Interface This chapter describes the ARM9E-S coprocessor interface. It contains the following sections: • About the coprocessor interface on page 6-2 • LDC/STC on page 6-4 • MCR/MRC on page 6-8 • MCRR/MRRC on page 6-10 ...
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ARM9E-S Coprocessor Interface 6.1 About the coprocessor interface The ARM9E-S supports the connection of coprocessors. All types of ARM coprocessors are supported. Coprocessors determine the instructions they need to execute using a pipeline follower in the coprocessor. As each instruction ...
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Examples of how a coprocessor must execute these instruction classes are given in: • LDC/STC on page 6-4 • MCR/MRC on page 6-8 • Interlocked MCR on page 6-12 • CDP on page 6-14. For the sake of clarity, all ...
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ARM9E-S Coprocessor Interface 6.2 LDC/STC The number of words transferred is determined by how the coprocessor drives the CHSD[1:0] and CHSE[1:0] buses. In the example ARM9E-S shown in Figure 6-1, four words of data are transferred. ARM processor pipeline CLK ...
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At the rising edge of CLK, if CLKEN is HIGH, and InMREQ is LOW, an instruction fetch is taking place, and INSTR[31:0] contains the fetched instruction on the next rising edge of the clock, when CLKEN is HIGH. This means ...
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ARM9E-S Coprocessor Interface If a coprocessor instruction busy-waits, PASS is asserted on every cycle until the coprocessor instruction is executed interrupt occurs during busy-waiting, PASS is driven LOW, and the coprocessor stops execution of the coprocessor instruction. A ...
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LAST 6.2.1 Coprocessor handshake encoding Table 6-1 shows how the handshake signals CHSD[1:0] and CHSE[1:0] are encoded. ARM DDI 0165B state of the PASS signal before actually committing to the instruction. For an or instruction, the coprocessor instruction drives the ...
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ARM9E-S Coprocessor Interface 6.3 MCR/MRC and MCR Figure 6-3. ARM processor pipeline CLK INSTR[31:0] InMREQ PASS CHSD[1:0] CHSE[1:0] WDATA[31:0] (MCR) RDATA[31:0] (MRC) First InMREQ is driven LOW to denote that the instruction on INSTR[31:0] is entering the decode stage of ...
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For any successive Execute cycles the CHSE[1:0] handshake bus is examined. When the LAST condition is observed, the instruction is committed. In the case of an WDATA[31:0] bus is driven with the register data. In the case of an RDATA[31:0] ...
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ARM9E-S Coprocessor Interface 6.4 MCRR/MRRC and MCRR Figure 6-4. ARM processor pipeline CLK INSTR[31:0] InMREQ PASS CHSD[1:0] CHSE[1:0] WDATA[31:0] (MCRR) RDATA[31:0] (MRRC) First InMREQ is driven LOW to denote that the instruction on INSTR[31:0] is entering the Decode stage of ...
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Execute cycle, and the second register data in the Memory cycle. In the case of an MRRC Memory cycles and written to the destination registers during the next cycle. ARM DDI 0165B , RDATA[31:0] is sampled at the ...
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ARM9E-S Coprocessor Interface 6.5 Interlocked MCR If the data for an first Decode cycle, the ARM9E-S pipeline interlocks for one or more cycles until the data is available. An example of this is where the register being transferred is the ...
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Interlocked MCRR If the data for an its first Decode cycle, the ARM9E-S pipeline interlocks for one or more cycles until the data is available. An example of this is where the register being transferred is the destination from ...
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ARM9E-S Coprocessor Interface 6.7 CDP instructions normally execute in a single cycle. Like all the previous cycles, CDP InMREQ is driven LOW to signal when an instruction is entering the Decode stage and again when it reaches the Execute stage ...
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The CDP by PASS. In the following cycle LATECANCEL is asserted. This causes the coprocessor to terminate execution of the instruction from causing state changes to the coprocessor. ARM DDI 0165B instruction enters the Execute stage of the pipeline and ...
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ARM9E-S Coprocessor Interface 6.8 Privileged instructions The coprocessor might restrict certain instructions for use in privileged modes only this, the coprocessor has to track the InTRANS output. Figure 6-8 shows how InTRANS changes after a mode change. Mode ...
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Busy-waiting and interrupts The coprocessor is permitted to stall, or busy-wait, the processor during the execution of a coprocessor instruction if, for example still busy with an earlier coprocessor instruction so, the coprocessor associated with ...
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ARM9E-S Coprocessor Interface 6.10 Coprocessor 15 MCRs Coprocessor 15 is typically reserved for use as a system control coprocessor. For an to coprocessor 15 possible to transfer the coprocessor data to the coprocessor on the IA and DA ...
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Connecting coprocessors A coprocessor in an ARM9E-S system needs to have 32-bit connections to: • data from memory (instruction stream and • write data from the ARM9E-S ( • read data to the ARM9E-S ( 6.11.1 Connecting a single ...
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ARM9E-S Coprocessor Interface The RDATA enable term (asel) is specially constructed to select the coprocessor output data during to the ARM9E-S RDATA and WDATA buses while still allowing tracing of data. STC 6.11.2 Connecting multiple coprocessors If you have multiple ...
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No external coprocessor If you are implementing a system that does not include any external coprocessors, you must tie both CHSD and CHSE to 10 (ABSENT). This indicates that no external coprocessors are present in the system. If any ...
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ARM9E-S Coprocessor Interface 6-22 Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0165B ...
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Chapter 7- Debug Interface and EmbeddedICE-RT This chapter describes the ARM9E-S debug interface in the following sections: • About the debug interface on page 7-2 • Debug systems on page 7-3 • Debug interface signals on page 7-9 • ARM9E-S ...
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Debug Interface and EmbeddedICE-RT 7.1 About the debug interface The ARM9E-S debug interface is based on IEEE Std. 1149.1-1990, Standard Test Access Port and Boundary-Scan Architecture. Refer to this standard for an explanation of the terms used in this chapter ...
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Debug systems The ARM9E-S forms one component of a debug system that interfaces from the high-level debugging performed by the user to the low-level interface supported by the ARM9E-S. Figure 7-1 shows a typical debug system. Debug Debug host ...
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Debug Interface and EmbeddedICE-RT 7.2.2 The protocol converter An interface, such as an RS232 or parallel connection, connects the debug host to the ARM9E-S development system. The messages broadcast over this connection must be converted to the interface signals of ...
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Scan chain 2 In halt mode debug a request on one of the external debug interface signals internal functional unit known as the EmbeddedICE-RT logic, forces the ARM9E-S into debug state. The events that activate debug are: ...
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Debug Interface and EmbeddedICE-RT 7.3 About EmbeddedICE-RT The ARM9E-S EmbeddedICE-RT logic provides integrated on-chip debug support for the ARM9E-S core. EmbeddedICE-RT is programmed serially using the ARM9E-S TAP controller. Figure 7-3 shows the relationship between the core, EmbeddedICE-RT, and the ...
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You can program one or both watchpoint units to halt the execution of instructions by the core. Execution halts when the values programmed into EmbeddedICE-RT match the values currently appearing on the address bus, data bus, and various control signals. ...
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Debug Interface and EmbeddedICE-RT 7.4 Disabling EmbeddedICE-RT You can disable EmbeddedICE-RT by setting the DBGEN input LOW. Hard wiring the DBGEN input LOW permanently disables all debug functionality. When DBGEN is LOW, it inhibits DBGDEWPT, DBGIEBKPT, and EDBGRQ to the ...
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Debug interface signals There are four primary external signals associated with the debug interface: • DBGIEBKPT, DBGDEWPT, and EDBGRQ are system requests for the ARM9E-S to enter debug state • DBGACK is used by the ARM9E-S to flag back ...
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Debug Interface and EmbeddedICE-RT A breakpointed instruction is allowed to enter the Execute stage of the pipeline, but any state change as a result of the instruction is prevented. All instructions prior to the breakpointed instruction complete as normal. If ...
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Watchpoints Entry into debug state following a watchpointed memory access is imprecise. This is necessary because of the nature of the pipeline. You can build external logic, such as external watchpoint comparators, to extend the functionality of the EmbeddedICE-RT ...
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Debug Interface and EmbeddedICE-RT Although instruction 5 enters the Execute stage not executed, and there is no state update as a result of this instruction. Once the debugging session is complete, normal continuation involves a return to instruction ...
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Watchpoints and exceptions If there is an abort with the data access as well as a watchpoint, the watchpoint condition is latched, the exception entry sequence is performed, and then the processor enters debug state. If there is an ...
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Debug Interface and EmbeddedICE-RT 7.6 ARM9E-S core clock domains The ARM9E-S has a single clock, CLK, that is qualified by two clock enables: • CLKEN controls access to the memory system • DBGTCKEN controls debug operations. During normal operation, CLKEN ...
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Determining the core and system state When the ARM9E debug state, you can examine the core and system state by forcing the load and store multiples into the instruction pipeline. Before you can examine the core and ...
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Debug Interface and EmbeddedICE-RT 7.8 The debug communications channel The ARM9E-S EmbeddedICE-RT logic contains a communications channel for passing information between the target and the host debugger. This is implemented as coprocessor 14. The communications channel comprises: • a 32-bit ...
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Debug comms channel control register The debug comms channel control register is read-only. synchronized handshaking between the processor and the debugger. The debug comms channel control register is shown in Figure 7-8. The function of each register bit is ...
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Debug Interface and EmbeddedICE-RT You can use the following instructions to access these registers: MRC p14, 0, Rd, c0, c0 This returns the debug comms control register into Rd. MCR p14, 0, Rn, c1, c0 This writes the value in ...
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A typical use of this bit monitor mode debug aware abort handler. This examines the DbgAbt bit to determine whether the abort was externally or internally generated. If the DbgAbt bit is set, the abort handler initiates ...
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Debug Interface and EmbeddedICE-RT Receiving a message from the debugger Transferring a message from the debugger to the processor is similar to sending a message to the debugger. In this case, the debugger polls the R bit of the debug ...
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Monitor mode debug ARM9E-S contains logic that allows the debugging of a system without stopping the core entirely. This allows the continued servicing of critical interrupt routines while the core is being interrogated by the debugger. Setting bit 4 ...
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Debug Interface and EmbeddedICE-RT If there is a possibility of false matches occurring during changes to the watchpoint registers, caused by old data in some registers and new data in others, then you must: 1. Disable the watchpoint unit using ...
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Chapter 8- Instruction Cycle Times This chapter gives the instruction cycle timings and illustrates interlock conditions present in the ARM9E-S design. It contains the following sections: • Instruction cycle count summary on page 8-3 • Introduction to detailed instruction cycle ...
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Instruction Cycle Times • Store double register on page 8-32 • Data swap on page 8-33 • PLD on page 8-35 • Software interrupt, undefined instruction, and exception entry on page 8-36 • Coprocessor data processing operation on page 8-37 ...
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Instruction cycle count summary Table 8-1 shows the key to the other tables in this chapter. Symbol Table 8-2 summarizes the ARM9E-S instruction cycle counts and bus activity when executing the ARM instruction ...
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Instruction Cycle Times Instruction Cycles 2 LDRD 3 LDRD 1 STR 2 STRD 2 LDM n LDM n+1 LDM n+4 LDM 5 LDM 2 STM STM n 2 SWP 3 SWP 1 PLD 3 B, BL, BX, BLX SWI, Undefined ...
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Instruction Cycles MRC (dest = PC) b+4 b+2 MRRC b+3 MRRC 2 MRS 1 MSR 3 MSR 2 MUL, MLA 3 MUL, MLA 4 MULS, MLAS 1 QADD, QDADD, QSUB, QDSUB 2 QADD, QDADD, QSUB, QDSUB 3 SMULL, UMULL, SMLAL, ...
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Instruction Cycle Times Instruction Cycles 1 SMULWx, SMLAWx 2 SMULWx, SMLAWx 2 SMLALxy 3 SMLALxy 8-6 Table 8-2 ARM instruction cycle counts (continued) Instruction Data bus bus 1S 1I 1S+1I 2I 1S+1I 2I 1S+2I 3I Copyright © 2000 ARM Limited. ...
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Introduction to detailed instruction cycle timings The pipelined architecture of ARM9E-S overlaps the execution of several instructions in different pipeline stages. The tables in this section show the number of cycles required by an instruction, once that instruction has ...
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Instruction Cycle Times 8.3 Branch and ARM branch with link Any ARM or Thumb branch, and an ARM branch with link operation takes three cycles: 1. During the first cycle, a branch instruction calculates the branch destination while performing a ...
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Thumb branch with link A Thumb Branch with Link ( instructions, and takes four cycles: 1. The first instruction acts as a simple data operation. It takes a single cycle to add the PC to the upper part of ...
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Instruction Cycle Times 8.5 Branch and exchange A Branch and Exchange ( or ARM 1. During the first cycle, the ARM9E-S extracts the branch destination and the new core state while performing a prefetch from the current PC. This prefetch ...
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Thumb Branch, Link, and Exchange <immediate> A Thumb Branch, Link, and Exchange immediate ( similar to a Thumb takes four cycles: 1. The first instruction acts as a simple data operation. It takes a single cycle to add the ...
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Instruction Cycle Times 8.7 Data operations A normal data operation executes in a single execute cycle except where the shift is determined by the contents of a register. A normal data operation requires up to two operands, that are read ...
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Cycle shift(Rs) shift (Rs) dest=pc ARM DDI 0165B Table 8-8 Data operation cycle timing (continued) InMREQ, IA ISEQ 1 pc+3i I cycle 2 pc+3i S cycle 1 pc+3i I cycle 2 pc’ N cycle 3 pc’+i S cycle 4 pc’+2i ...
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Instruction Cycle Times 8.8 MRS An MRS pending state changes to the PSR to be made. The second cycle passes the PSR register through the ALU so that it can be written to the destination register. The MRS Table 8-9 ...
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MSR operations An MSR CPSR, and three cycles if it updates other parts of the PSR. instructions can only be executed in ARM state. MSR Table 8-10 shows the cycle timings for MSR operations. Cycle MSR flags MSR other ...
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Instruction Cycle Times 8.10 Multiply and multiply accumulate The multiply instructions make use of special hardware that implements integer multiplication. All cycles except the last are internal. During the first (Execute) stage of a multiply instruction, the multiplier and multiplicand ...
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Table 8-11 shows the cycle timing for interlocks. Cycle Normal Interlock The MULS generate interlocks in following instructions. Table 8-12 shows the cycle timing for Cycle ARM DDI 0165B MUL InMREQ, IA ISEQ 1 pc+3i I ...
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Instruction Cycle Times Table 8-13 shows the cycle timing for with and without interlocks. Cycle Normal Interlock The SMULLS execute, and cannot generate interlocks in following instructions. Table 8-14 shows the cycle timing for the instructions. Cycle ...
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Table 8-15 shows the cycle timing for instructions with and without interlocks. Cycle Normal Interlock Table 8-16 shows the cycle timing for interlocks. Cycle Normal Interlock ARM DDI 0165B SMULxy Table 8-15 SMULxy, SMLAxy, SMULWy, and SMLAWy cycle timing InMREQ, ...
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Instruction Cycle Times 8.11 QADD, QDADD, QSUB, and QDSUB This class of instructions normally takes one cycle to execute and is only available in ARM state. 8.11.1 Interlocks The instructions in this class use both the Execute and Memory stages ...
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Load register A load register operation typically occupies the Execute stage for one cycle. There might be a number of cycles before the loaded value is available for later instructions. A load to the PC occupies the Execute stage ...
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Instruction Cycle Times For example, the following sequence incurs a two-cycle interlock on the first instruction, but the second LDRB ADD ADD A two-cycle interlock refers to the number of unwaited ARM9E-S clock cycles to which the interlock applies. If ...
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The following example incurs a second-cycle interlock: LDR STMIA A second-cycle interlock can be incurred on the first word of data stored by an instruction or during the first cycle of a register controlled shift. The following example does not ...
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Instruction Cycle Times Table 8-19 shows the cycle timing for load operations resulting in simple interlocks. Cycle Single-cycle interlock Two-cycle interlock With more complicated interlock cases you cannot consider the load instruction in isolation. This is because in these cases ...
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Table 8-21 shows the cycle timing for the following code sequence: LDRB STMIA Cycle IA LDRB r0, [r2] 1 pc+3i STMIA r3, {r0-r1} 2 pc+4i 3 pc+4i 4 pc+4i ARM DDI 0165B r0, [r2] r3, {r0-r1} Table 8-21 Example sequence ...
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Instruction Cycle Times 8.13 Store register A store register operation executes in a single cycle. During the Execute cycle, the store address is calculated, and the data to be stored is read onto the C bus. Table 8-22 shows the ...
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Load multiple registers A load multiple ( registers transferred and whether the the list of registers transferred. 1. During the first cycle, the ARM9E-S calculates the address of the first word to be transferred, while performing ...
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Instruction Cycle Times The LDM Cycle 1 register (not PC registers 1 (n > (not PC register 1 dest= registers 1 (n > (incl pc) ...
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Cycle n registers 1 (n > cycle interlock ARM DDI 0165B InMREQ, IA INSTR ISEQ pc+3i I cycle (pc+2i) pc+3i I cycle - pc+3i I cycle - pc+3i I cycle - pc+3i ...
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Instruction Cycle Times 8.15 Store multiple registers Store multiple ( instructions. 1. During the first cycle, the ARM9E-S calculates the address of the first word to be transferred, while performing an instruction prefetch and also calculating the new value for ...
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Load double register The LDRD multiple registers on page 8-27 and the appropriate entries in Table 8-23 on page 8-28. ARM DDI 0165B instruction behaves in the same way as an Copyright © 2000 ARM Limited. All rights reserved. ...
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Instruction Cycle Times 8.17 Store double register The STRD multiple registers on page 8-30 and the appropriate entries in Table 8-24 on page 8-30. 8-32 instruction behaves in the same way as an Copyright © 2000 ARM Limited. All rights ...
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Data swap A data swap is similar to a back-to-back load and store instruction. The data is read from external memory in the second cycle and the contents of the register are written to the external memory in the ...
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Instruction Cycle Times Cycle IA 2 cycle interlock 1 pc+3i 2 pc+3i 3 pc+3i 4 pc+3i 8-34 Table 8-25 Data swap cycle timing (continued) InMREQ, INSTR ISEQ I cycle (pc+2i) I cycle - I cycle - S cycle - (pc+3i) ...
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PLD A PLD address is calculated and broadcast on DA[31:0]. DnMREQ and DSEQ indicate an internal cycle, and DnSPEC is asserted. Table 8-26 shows the cycle timings for PLD instructions. Cycle 1 ARM DDI 0165B operation executes in a ...
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Instruction Cycle Times 8.20 Software interrupt, undefined instruction, and exception entry Exceptions, software interrupts (SWIs), and undefined instructions force the specific value and refill the instruction pipeline from this address: 1. During the first cycle, the ARM9E-S ...
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Coprocessor data processing operation A coprocessor data (CDP) operation is a request from the ARM9E-S for the coprocessor to initiate some action. There is no need for the coprocessor to complete the action immediately, but the coprocessor must commit ...
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Instruction Cycle Times 8.22 Load coprocessor register (from memory) The load coprocessor ( to a coprocessor. The coprocessor commits to the transfer only when it is ready to accept the data. The coprocessor indicates that it is ready for the ...
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Cycle IA IREQ m registers (m > pc+3i I cycle ready 2 pc+3i I cycle . pc+3i I cycle m-1 pc+3i I cycle m pc+3i S cycle m registers (m > pc+3i I cycle not ready ...
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Instruction Cycle Times 8.23 Store coprocessor register (to memory) The store coprocessor ( coprocessor to memory. The coprocessor commits to the transfer only when it is ready to write the data. The coprocessor indicates that it is ready for the ...